#define GAUDI_MASKS_H_
#include "asic_reg/gaudi_regs.h"
+#include <linux/bitfield.h>
/* Useful masks for bits in various registers */
#define PCI_DMA_QMAN_ENABLE (\
- (0xF << DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
- (0xF << DMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
- (0xF << DMA0_QM_GLBL_CFG0_CP_EN_SHIFT))
+ (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF)))
#define QMAN_EXTERNAL_MAKE_TRUSTED (\
- (0xF << DMA0_QM_GLBL_PROT_PQF_SHIFT) | \
- (0xF << DMA0_QM_GLBL_PROT_CQF_SHIFT) | \
- (0xF << DMA0_QM_GLBL_PROT_CP_SHIFT) | \
- (0x1 << DMA0_QM_GLBL_PROT_ERR_SHIFT))
+ (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
#define QMAN_INTERNAL_MAKE_TRUSTED (\
- (0xF << DMA0_QM_GLBL_PROT_PQF_SHIFT) | \
- (0x1 << DMA0_QM_GLBL_PROT_ERR_SHIFT))
+ (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
#define HBM_DMA_QMAN_ENABLE (\
- (0xF << DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
- (0x1F << DMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
- (0x1F << DMA0_QM_GLBL_CFG0_CP_EN_SHIFT))
+ (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
#define QMAN_MME_ENABLE (\
- (0xF << MME0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
- (0x1F << MME0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
- (0x1F << MME0_QM_GLBL_CFG0_CP_EN_SHIFT))
+ (FIELD_PREP(MME0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
+ (FIELD_PREP(MME0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
+ (FIELD_PREP(MME0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
#define QMAN_TPC_ENABLE (\
- (0xF << TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
- (0x1F << TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
- (0x1F << TPC0_QM_GLBL_CFG0_CP_EN_SHIFT))
+ (FIELD_PREP(TPC0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
+ (FIELD_PREP(TPC0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
+ (FIELD_PREP(TPC0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
#define QMAN_UPPER_CP_CGM_PWR_GATE_EN (\
- (0x20 << DMA0_QM_CGM_CFG_IDLE_TH_SHIFT) | \
- (0xA << DMA0_QM_CGM_CFG_G2F_TH_SHIFT) | \
- (0x10 << DMA0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT) | \
- (1 << DMA0_QM_CGM_CFG_EN_SHIFT))
+ (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \
+ (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \
+ (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0x10)) | \
+ (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))
#define QMAN_COMMON_CP_CGM_PWR_GATE_EN (\
- (0x20 << DMA0_QM_CGM_CFG_IDLE_TH_SHIFT) | \
- (0xA << DMA0_QM_CGM_CFG_G2F_TH_SHIFT) | \
- (0xF << DMA0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT) | \
- (1 << DMA0_QM_CGM_CFG_EN_SHIFT))
+ (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \
+ (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \
+ (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))
#define PCI_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\
- (0xF << DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \
- (0xF << DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \
- (0xF << DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT))
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF)))
#define PCI_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\
- (0xF << DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \
- (0xF << DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \
- (0xF << DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT))
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF)))
#define HBM_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\
- (0xF << DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \
- (0x1F << DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \
- (0x1F << DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT))
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
#define HBM_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\
- (0xF << DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \
- (0x1F << DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \
- (0x1F << DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT))
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)))
#define TPC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\
- (0xF << TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \
- (0x1F << TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \
- (0x1F << TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT))
+ (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
+ (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
+ (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
#define TPC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\
- (0xF << TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \
- (0x1F << TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \
- (0x1F << TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT))
+ (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
+ (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
+ (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)))
#define MME_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\
- (0xF << MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \
- (0x1F << MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \
- (0x1F << MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT))
+ (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
+ (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
+ (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
#define MME_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\
- (0xF << MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \
- (0x1F << MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \
- (0x1F << MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT))
+ (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
+ (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
+ (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)))
-#define QMAN_CGM1_PWR_GATE_EN (0xA << DMA0_QM_CGM_CFG1_MASK_TH_SHIFT)
+#define QMAN_CGM1_PWR_GATE_EN (FIELD_PREP(DMA0_QM_CGM_CFG1_MASK_TH_MASK, 0xA))
/* RESET registers configuration */
-#define CFG_RST_L_PSOC_SHIFT 0
-#define CFG_RST_L_PCIE_SHIFT 1
-#define CFG_RST_L_PCIE_IF_SHIFT 2
-#define CFG_RST_L_HBM_S_PLL_SHIFT 3
-#define CFG_RST_L_TPC_S_PLL_SHIFT 4
-#define CFG_RST_L_MME_S_PLL_SHIFT 5
-#define CFG_RST_L_CPU_PLL_SHIFT 6
-#define CFG_RST_L_PCIE_PLL_SHIFT 7
-#define CFG_RST_L_NIC_S_PLL_SHIFT 8
-#define CFG_RST_L_HBM_N_PLL_SHIFT 9
-#define CFG_RST_L_TPC_N_PLL_SHIFT 10
-#define CFG_RST_L_MME_N_PLL_SHIFT 11
-#define CFG_RST_L_NIC_N_PLL_SHIFT 12
-#define CFG_RST_L_DMA_W_PLL_SHIFT 13
-#define CFG_RST_L_SIF_W_PLL_SHIFT 14
-#define CFG_RST_L_MESH_W_PLL_SHIFT 15
-#define CFG_RST_L_SRAM_W_PLL_SHIFT 16
-#define CFG_RST_L_DMA_E_PLL_SHIFT 17
-#define CFG_RST_L_SIF_E_PLL_SHIFT 18
-#define CFG_RST_L_MESH_E_PLL_SHIFT 19
-#define CFG_RST_L_SRAM_E_PLL_SHIFT 20
-#define CFG_RST_L_IF_1_SHIFT 21
-#define CFG_RST_L_IF_0_SHIFT 22
-#define CFG_RST_L_IF_2_SHIFT 23
-#define CFG_RST_L_IF_3_SHIFT 24
-#define CFG_RST_L_TPC_0_SHIFT 25
-#define CFG_RST_L_TPC_1_SHIFT 26
-#define CFG_RST_L_TPC_2_SHIFT 27
-#define CFG_RST_L_TPC_3_SHIFT 28
-#define CFG_RST_L_TPC_4_SHIFT 29
-#define CFG_RST_L_TPC_5_SHIFT 30
-#define CFG_RST_L_TPC_6_SHIFT 31
-#define CFG_RST_H_TPC_7_SHIFT 0
-#define CFG_RST_H_MME_0_SHIFT 1
-#define CFG_RST_H_MME_1_SHIFT 2
-#define CFG_RST_H_MME_2_SHIFT 3
-#define CFG_RST_H_MME_3_SHIFT 4
-#define CFG_RST_H_HBM_0_SHIFT 5
-#define CFG_RST_H_HBM_1_SHIFT 6
-#define CFG_RST_H_HBM_2_SHIFT 7
-#define CFG_RST_H_HBM_3_SHIFT 8
-#define CFG_RST_H_NIC_0_SHIFT 9
-#define CFG_RST_H_NIC_1_SHIFT 10
-#define CFG_RST_H_NIC_2_SHIFT 11
-#define CFG_RST_H_NIC_3_SHIFT 12
-#define CFG_RST_H_NIC_4_SHIFT 13
-#define CFG_RST_H_SM_0_SHIFT 14
-#define CFG_RST_H_SM_1_SHIFT 15
-#define CFG_RST_H_SM_2_SHIFT 16
-#define CFG_RST_H_SM_3_SHIFT 17
-#define CFG_RST_H_DMA_0_SHIFT 18
-#define CFG_RST_H_DMA_1_SHIFT 19
-#define CFG_RST_H_CPU_SHIFT 20
-#define CFG_RST_H_MMU_SHIFT 21
-
-
-#define CFG_RST_H_DMA_MASK ((1 << CFG_RST_H_DMA_0_SHIFT) | \
- (1 << CFG_RST_H_DMA_1_SHIFT))
-
-#define CFG_RST_H_CPU_MASK (1 << CFG_RST_H_CPU_SHIFT)
-#define CFG_RST_H_MMU_MASK (1 << CFG_RST_H_MMU_SHIFT)
-
-#define CFG_RST_H_HBM_MASK ((1 << CFG_RST_H_HBM_0_SHIFT) | \
- (1 << CFG_RST_H_HBM_1_SHIFT) | \
- (1 << CFG_RST_H_HBM_2_SHIFT) | \
- (1 << CFG_RST_H_HBM_3_SHIFT))
-
-#define CFG_RST_H_NIC_MASK ((1 << CFG_RST_H_NIC_0_SHIFT) | \
- (1 << CFG_RST_H_NIC_1_SHIFT) | \
- (1 << CFG_RST_H_NIC_2_SHIFT) | \
- (1 << CFG_RST_H_NIC_3_SHIFT) | \
- (1 << CFG_RST_H_NIC_4_SHIFT))
-
-#define CFG_RST_H_SM_MASK ((1 << CFG_RST_H_SM_0_SHIFT) | \
- (1 << CFG_RST_H_SM_1_SHIFT) | \
- (1 << CFG_RST_H_SM_2_SHIFT) | \
- (1 << CFG_RST_H_SM_3_SHIFT))
-
-#define CFG_RST_H_MME_MASK ((1 << CFG_RST_H_MME_0_SHIFT) | \
- (1 << CFG_RST_H_MME_1_SHIFT) | \
- (1 << CFG_RST_H_MME_2_SHIFT) | \
- (1 << CFG_RST_H_MME_3_SHIFT))
-
-#define CFG_RST_L_PSOC_MASK (1 << CFG_RST_L_PSOC_SHIFT)
-
-#define CFG_RST_L_IF_MASK ((1 << CFG_RST_L_IF_0_SHIFT) | \
- (1 << CFG_RST_L_IF_1_SHIFT) | \
- (1 << CFG_RST_L_IF_2_SHIFT) | \
- (1 << CFG_RST_L_IF_3_SHIFT))
-
-#define CFG_RST_L_TPC_MASK ((1 << CFG_RST_L_TPC_0_SHIFT) | \
- (1 << CFG_RST_L_TPC_1_SHIFT) | \
- (1 << CFG_RST_L_TPC_2_SHIFT) | \
- (1 << CFG_RST_L_TPC_3_SHIFT) | \
- (1 << CFG_RST_L_TPC_4_SHIFT) | \
- (1 << CFG_RST_L_TPC_5_SHIFT) | \
- (1 << CFG_RST_L_TPC_6_SHIFT))
-
-#define CFG_RST_H_TPC_MASK (1 << CFG_RST_H_TPC_7_SHIFT)
-
-#define CA53_RESET (1 << CFG_RST_H_CPU_SHIFT)
+#define CFG_RST_L_PSOC_MASK BIT_MASK(0)
+#define CFG_RST_L_PCIE_MASK BIT_MASK(1)
+#define CFG_RST_L_PCIE_IF_MASK BIT_MASK(2)
+#define CFG_RST_L_HBM_S_PLL_MASK BIT_MASK(3)
+#define CFG_RST_L_TPC_S_PLL_MASK BIT_MASK(4)
+#define CFG_RST_L_MME_S_PLL_MASK BIT_MASK(5)
+#define CFG_RST_L_CPU_PLL_MASK BIT_MASK(6)
+#define CFG_RST_L_PCIE_PLL_MASK BIT_MASK(7)
+#define CFG_RST_L_NIC_S_PLL_MASK BIT_MASK(8)
+#define CFG_RST_L_HBM_N_PLL_MASK BIT_MASK(9)
+#define CFG_RST_L_TPC_N_PLL_MASK BIT_MASK(10)
+#define CFG_RST_L_MME_N_PLL_MASK BIT_MASK(11)
+#define CFG_RST_L_NIC_N_PLL_MASK BIT_MASK(12)
+#define CFG_RST_L_DMA_W_PLL_MASK BIT_MASK(13)
+#define CFG_RST_L_SIF_W_PLL_MASK BIT_MASK(14)
+#define CFG_RST_L_MESH_W_PLL_MASK BIT_MASK(15)
+#define CFG_RST_L_SRAM_W_PLL_MASK BIT_MASK(16)
+#define CFG_RST_L_DMA_E_PLL_MASK BIT_MASK(17)
+#define CFG_RST_L_SIF_E_PLL_MASK BIT_MASK(18)
+#define CFG_RST_L_MESH_E_PLL_MASK BIT_MASK(19)
+#define CFG_RST_L_SRAM_E_PLL_MASK BIT_MASK(20)
+
+#define CFG_RST_L_IF_1_MASK BIT_MASK(21)
+#define CFG_RST_L_IF_0_MASK BIT_MASK(22)
+#define CFG_RST_L_IF_2_MASK BIT_MASK(23)
+#define CFG_RST_L_IF_3_MASK BIT_MASK(24)
+#define CFG_RST_L_IF_MASK GENMASK(24, 21)
+
+#define CFG_RST_L_TPC_0_MASK BIT_MASK(25)
+#define CFG_RST_L_TPC_1_MASK BIT_MASK(26)
+#define CFG_RST_L_TPC_2_MASK BIT_MASK(27)
+#define CFG_RST_L_TPC_3_MASK BIT_MASK(28)
+#define CFG_RST_L_TPC_4_MASK BIT_MASK(29)
+#define CFG_RST_L_TPC_5_MASK BIT_MASK(30)
+#define CFG_RST_L_TPC_6_MASK BIT_MASK(31)
+#define CFG_RST_L_TPC_MASK GENMASK(31, 25)
+
+#define CFG_RST_H_TPC_7_MASK BIT_MASK(0)
+
+#define CFG_RST_H_MME_0_MASK BIT_MASK(1)
+#define CFG_RST_H_MME_1_MASK BIT_MASK(2)
+#define CFG_RST_H_MME_2_MASK BIT_MASK(3)
+#define CFG_RST_H_MME_3_MASK BIT_MASK(4)
+#define CFG_RST_H_MME_MASK GENMASK(4, 1)
+
+#define CFG_RST_H_HBM_0_MASK BIT_MASK(5)
+#define CFG_RST_H_HBM_1_MASK BIT_MASK(6)
+#define CFG_RST_H_HBM_2_MASK BIT_MASK(7)
+#define CFG_RST_H_HBM_3_MASK BIT_MASK(8)
+#define CFG_RST_H_HBM_MASK GENMASK(8, 5)
+
+#define CFG_RST_H_NIC_0_MASK BIT_MASK(9)
+#define CFG_RST_H_NIC_1_MASK BIT_MASK(10)
+#define CFG_RST_H_NIC_2_MASK BIT_MASK(11)
+#define CFG_RST_H_NIC_3_MASK BIT_MASK(12)
+#define CFG_RST_H_NIC_4_MASK BIT_MASK(13)
+#define CFG_RST_H_NIC_MASK GENMASK(13, 9)
+
+#define CFG_RST_H_SM_0_MASK BIT_MASK(14)
+#define CFG_RST_H_SM_1_MASK BIT_MASK(15)
+#define CFG_RST_H_SM_2_MASK BIT_MASK(16)
+#define CFG_RST_H_SM_3_MASK BIT_MASK(17)
+#define CFG_RST_H_SM_MASK GENMASK(17, 14)
+
+#define CFG_RST_H_DMA_0_MASK BIT_MASK(18)
+#define CFG_RST_H_DMA_1_MASK BIT_MASK(19)
+#define CFG_RST_H_DMA_MASK GENMASK(19, 18)
+
+#define CFG_RST_H_CPU_MASK BIT_MASK(20)
+#define CFG_RST_H_MMU_MASK BIT_MASK(21)
#define UNIT_RST_L_PSOC_SHIFT 0
#define UNIT_RST_L_PCIE_SHIFT 1
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