Merge tag 'irq-core-2024-03-10' of git://git.kernel.org/pub/scm/linux/kernel/git...

[linux-2.6-microblaze.git] / drivers / irqchip / irq-gic.c

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 412196a..98aa383 100644 (file)
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -162,11 +162,6 @@ static inline void __iomem *gic_cpu_base(struct irq_data *d)
        return gic_data_cpu_base(gic_data);
 }
 
-static inline unsigned int gic_irq(struct irq_data *d)
-{
-       return d->hwirq;
-}
-
 static inline bool cascading_gic_irq(struct irq_data *d)
 {
        void *data = irq_data_get_irq_handler_data(d);
@@ -183,14 +178,16 @@ static inline bool cascading_gic_irq(struct irq_data *d)
  */
 static void gic_poke_irq(struct irq_data *d, u32 offset)
 {
-       u32 mask = 1 << (gic_irq(d) % 32);
-       writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
+       u32 mask = 1 << (irqd_to_hwirq(d) % 32);
+
+       writel_relaxed(mask, gic_dist_base(d) + offset + (irqd_to_hwirq(d) / 32) * 4);
 }
 
 static int gic_peek_irq(struct irq_data *d, u32 offset)
 {
-       u32 mask = 1 << (gic_irq(d) % 32);
-       return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
+       u32 mask = 1 << (irqd_to_hwirq(d) % 32);
+
+       return !!(readl_relaxed(gic_dist_base(d) + offset + (irqd_to_hwirq(d) / 32) * 4) & mask);
 }
 
 static void gic_mask_irq(struct irq_data *d)
@@ -220,7 +217,7 @@ static void gic_unmask_irq(struct irq_data *d)
 
 static void gic_eoi_irq(struct irq_data *d)
 {
-       u32 hwirq = gic_irq(d);
+       irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
        if (hwirq < 16)
                hwirq = this_cpu_read(sgi_intid);
@@ -230,7 +227,7 @@ static void gic_eoi_irq(struct irq_data *d)
 
 static void gic_eoimode1_eoi_irq(struct irq_data *d)
 {
-       u32 hwirq = gic_irq(d);
+       irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
        /* Do not deactivate an IRQ forwarded to a vcpu. */
        if (irqd_is_forwarded_to_vcpu(d))
@@ -293,8 +290,8 @@ static int gic_irq_get_irqchip_state(struct irq_data *d,
 
 static int gic_set_type(struct irq_data *d, unsigned int type)
 {
+       irq_hw_number_t gicirq = irqd_to_hwirq(d);
        void __iomem *base = gic_dist_base(d);
-       unsigned int gicirq = gic_irq(d);
        int ret;
 
        /* Interrupt configuration for SGIs can't be changed */
@@ -309,7 +306,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
        ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL);
        if (ret && gicirq < 32) {
                /* Misconfigured PPIs are usually not fatal */
-               pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16);
+               pr_warn("GIC: PPI%ld is secure or misconfigured\n", gicirq - 16);
                ret = 0;
        }
 
@@ -319,7 +316,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
 {
        /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
-       if (cascading_gic_irq(d) || gic_irq(d) < 16)
+       if (cascading_gic_irq(d) || irqd_to_hwirq(d) < 16)
                return -EINVAL;
 
        if (vcpu)
@@ -796,7 +793,7 @@ static void rmw_writeb(u8 bval, void __iomem *addr)
 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
                            bool force)
 {
-       void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d);
+       void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + irqd_to_hwirq(d);
        struct gic_chip_data *gic = irq_data_get_irq_chip_data(d);
        unsigned int cpu;