drm/i915: Create stolen memory region from local memory

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7146cd0..da73dc9 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -487,6 +487,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define GAB_CTL                                _MMIO(0x24000)
 #define   GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8)
 
+#define GU_CNTL                                _MMIO(0x101010)
+#define   LMEM_INIT                    REG_BIT(7)
+
 #define GEN6_STOLEN_RESERVED           _MMIO(0x1082C0)
 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
@@ -1874,10 +1877,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _ICL_COMBOPHY_B                        0x6C000
 #define _EHL_COMBOPHY_C                        0x160000
 #define _RKL_COMBOPHY_D                        0x161000
+#define _ADL_COMBOPHY_E                        0x16B000
+
 #define _ICL_COMBOPHY(phy)             _PICK(phy, _ICL_COMBOPHY_A, \
                                              _ICL_COMBOPHY_B, \
                                              _EHL_COMBOPHY_C, \
-                                             _RKL_COMBOPHY_D)
+                                             _RKL_COMBOPHY_D, \
+                                             _ADL_COMBOPHY_E)
 
 /* CNL/ICL Port CL_DW registers */
 #define _ICL_PORT_CL_DW(dw, phy)       (_ICL_COMBOPHY(phy) + \
@@ -2712,6 +2718,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
 #define RING_CTX_TIMESTAMP(base)       _MMIO((base) + 0x3a8) /* gen8+ */
 
+#define VDBOX_CGCTL3F10(base)          _MMIO((base) + 0x3f10)
+#define   IECPUNIT_CLKGATE_DIS         REG_BIT(22)
+
 #define ERROR_GEN6     _MMIO(0x40a0)
 #define GEN7_ERR_INT   _MMIO(0x44040)
 #define   ERR_INT_POISON               (1 << 31)
@@ -2927,7 +2936,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MBUS_BBOX_CTL_S2               _MMIO(0x45044)
 
 #define HDPORT_STATE                   _MMIO(0x45050)
-#define   HDPORT_DPLL_USED_MASK                REG_GENMASK(14, 12)
+#define   HDPORT_DPLL_USED_MASK                REG_GENMASK(15, 12)
 #define   HDPORT_DDI_USED(phy)         REG_BIT(2 * (phy) + 1)
 #define   HDPORT_ENABLED               REG_BIT(0)
 
@@ -3316,7 +3325,18 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 
 #define ILK_DISPLAY_CHICKEN1   _MMIO(0x42000)
 #define   ILK_FBCQ_DIS         (1 << 22)
-#define          ILK_PABSTRETCH_DIS    (1 << 21)
+#define   ILK_PABSTRETCH_DIS   REG_BIT(21)
+#define   ILK_SABSTRETCH_DIS   REG_BIT(20)
+#define   IVB_PRI_STRETCH_MAX_MASK     REG_GENMASK(21, 20)
+#define   IVB_PRI_STRETCH_MAX_X8       REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
+#define   IVB_PRI_STRETCH_MAX_X4       REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
+#define   IVB_PRI_STRETCH_MAX_X2       REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
+#define   IVB_PRI_STRETCH_MAX_X1       REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
+#define   IVB_SPR_STRETCH_MAX_MASK     REG_GENMASK(19, 18)
+#define   IVB_SPR_STRETCH_MAX_X8       REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
+#define   IVB_SPR_STRETCH_MAX_X4       REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
+#define   IVB_SPR_STRETCH_MAX_X2       REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
+#define   IVB_SPR_STRETCH_MAX_X1       REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
 
 
 /*
@@ -8039,6 +8059,16 @@ enum {
 
 #define _CHICKEN_PIPESL_1_A    0x420b0
 #define _CHICKEN_PIPESL_1_B    0x420b4
+#define  HSW_PRI_STRETCH_MAX_MASK      REG_GENMASK(28, 27)
+#define  HSW_PRI_STRETCH_MAX_X8                REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
+#define  HSW_PRI_STRETCH_MAX_X4                REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
+#define  HSW_PRI_STRETCH_MAX_X2                REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
+#define  HSW_PRI_STRETCH_MAX_X1                REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
+#define  HSW_SPR_STRETCH_MAX_MASK      REG_GENMASK(26, 25)
+#define  HSW_SPR_STRETCH_MAX_X8                REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
+#define  HSW_SPR_STRETCH_MAX_X4                REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
+#define  HSW_SPR_STRETCH_MAX_X2                REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
+#define  HSW_SPR_STRETCH_MAX_X1                REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
 #define  HSW_FBCQ_DIS                  (1 << 22)
 #define  BDW_DPRS_MASK_VBLANK_SRD      (1 << 0)
 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
@@ -10357,7 +10387,7 @@ enum skl_power_gate {
 
 /* ICL Clocks */
 #define ICL_DPCLKA_CFGCR0                      _MMIO(0x164280)
-#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)    (1 << _PICK(phy, 10, 11, 24))
+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)    (1 << _PICK(phy, 10, 11, 24, 4, 5))
 #define  RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)    REG_BIT((phy) + 10)
 #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \
                                                       (tc_port) + 12 : \
@@ -10392,14 +10422,38 @@ enum skl_power_gate {
 #define   DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy) \
        (((clk_sel) >> DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) + _DG1_PHY_DPLL_MAP(phy))
 
+/* ADLS Clocks */
+#define _ADLS_DPCLKA_CFGCR0                    0x164280
+#define _ADLS_DPCLKA_CFGCR1                    0x1642BC
+#define ADLS_DPCLKA_CFGCR(phy)                 _MMIO_PHY((phy) / 3, \
+                                                         _ADLS_DPCLKA_CFGCR0, \
+                                                         _ADLS_DPCLKA_CFGCR1)
+#define  ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)              (((phy) % 3) * 2)
+/* ADLS DPCLKA_CFGCR0 DDI mask */
+#define  ADLS_DPCLKA_DDII_SEL_MASK                     REG_GENMASK(5, 4)
+#define  ADLS_DPCLKA_DDIB_SEL_MASK                     REG_GENMASK(3, 2)
+#define  ADLS_DPCLKA_DDIA_SEL_MASK                     REG_GENMASK(1, 0)
+/* ADLS DPCLKA_CFGCR1 DDI mask */
+#define  ADLS_DPCLKA_DDIK_SEL_MASK                     REG_GENMASK(3, 2)
+#define  ADLS_DPCLKA_DDIJ_SEL_MASK                     REG_GENMASK(1, 0)
+#define  ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy)       _PICK((phy), \
+                                                       ADLS_DPCLKA_DDIA_SEL_MASK, \
+                                                       ADLS_DPCLKA_DDIB_SEL_MASK, \
+                                                       ADLS_DPCLKA_DDII_SEL_MASK, \
+                                                       ADLS_DPCLKA_DDIJ_SEL_MASK, \
+                                                       ADLS_DPCLKA_DDIK_SEL_MASK)
+
 /* CNL PLL */
 #define DPLL0_ENABLE           0x46010
 #define DPLL1_ENABLE           0x46014
+#define _ADLS_DPLL2_ENABLE     0x46018
+#define _ADLS_DPLL3_ENABLE     0x46030
 #define  PLL_ENABLE            (1 << 31)
 #define  PLL_LOCK              (1 << 30)
 #define  PLL_POWER_ENABLE      (1 << 27)
 #define  PLL_POWER_STATE       (1 << 26)
-#define CNL_DPLL_ENABLE(pll)   _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
+#define CNL_DPLL_ENABLE(pll)   _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+                                          _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
 
 #define TBT_PLL_ENABLE         _MMIO(0x46020)
 
@@ -10645,6 +10699,21 @@ enum skl_power_gate {
                                                   _DG1_DPLL2_CFGCR1, \
                                                   _DG1_DPLL3_CFGCR1)
 
+/* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
+#define _ADLS_DPLL3_CFGCR0             0x1642C0
+#define _ADLS_DPLL4_CFGCR0             0x164294
+#define ADLS_DPLL_CFGCR0(pll)          _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
+                                                  _TGL_DPLL1_CFGCR0, \
+                                                  _ADLS_DPLL4_CFGCR0, \
+                                                  _ADLS_DPLL3_CFGCR0)
+
+#define _ADLS_DPLL3_CFGCR1             0x1642C4
+#define _ADLS_DPLL4_CFGCR1             0x164298
+#define ADLS_DPLL_CFGCR1(pll)          _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
+                                                  _TGL_DPLL1_CFGCR1, \
+                                                  _ADLS_DPLL4_CFGCR1, \
+                                                  _ADLS_DPLL3_CFGCR1)
+
 #define _DKL_PHY1_BASE                 0x168000
 #define _DKL_PHY2_BASE                 0x169000
 #define _DKL_PHY3_BASE                 0x16A000
@@ -11406,6 +11475,9 @@ enum skl_power_gate {
 #define  BIG_JOINER_ENABLE                     (1 << 29)
 #define  MASTER_BIG_JOINER_ENABLE              (1 << 28)
 #define  VGA_CENTERING_ENABLE                  (1 << 27)
+#define  SPLITTER_CONFIGURATION_MASK           REG_GENMASK(26, 25)
+#define  SPLITTER_CONFIGURATION_2_SEGMENT      REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
+#define  SPLITTER_CONFIGURATION_4_SEGMENT      REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
 
 #define _ICL_PIPE_DSS_CTL2_PB                  0x78204
 #define _ICL_PIPE_DSS_CTL2_PC                  0x78404
@@ -12121,6 +12193,9 @@ enum skl_power_gate {
 
 #define GEN12_GLOBAL_MOCS(i)   _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
 
+#define GEN12_GSMBASE                  _MMIO(0x108100)
+#define GEN12_DSMBASE                  _MMIO(0x1080C0)
+
 /* gamt regs */
 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */