Merge tag 'drm-intel-next-2021-08-10-1' of git://anongit.freedesktop.org/drm/drm...

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 680accc..167eaa8 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -395,10 +395,18 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define  GEN11_GRDOM_MEDIA2            (1 << 6)
 #define  GEN11_GRDOM_MEDIA3            (1 << 7)
 #define  GEN11_GRDOM_MEDIA4            (1 << 8)
+#define  GEN11_GRDOM_MEDIA5            (1 << 9)
+#define  GEN11_GRDOM_MEDIA6            (1 << 10)
+#define  GEN11_GRDOM_MEDIA7            (1 << 11)
+#define  GEN11_GRDOM_MEDIA8            (1 << 12)
 #define  GEN11_GRDOM_VECS              (1 << 13)
 #define  GEN11_GRDOM_VECS2             (1 << 14)
+#define  GEN11_GRDOM_VECS3             (1 << 15)
+#define  GEN11_GRDOM_VECS4             (1 << 16)
 #define  GEN11_GRDOM_SFC0              (1 << 17)
 #define  GEN11_GRDOM_SFC1              (1 << 18)
+#define  GEN11_GRDOM_SFC2              (1 << 19)
+#define  GEN11_GRDOM_SFC3              (1 << 20)
 
 #define  GEN11_VCS_SFC_RESET_BIT(instance)     (GEN11_GRDOM_SFC0 << ((instance) >> 1))
 #define  GEN11_VECS_SFC_RESET_BIT(instance)    (GEN11_GRDOM_SFC0 << (instance))
@@ -2507,9 +2515,15 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define GEN11_BSD2_RING_BASE   0x1c4000
 #define GEN11_BSD3_RING_BASE   0x1d0000
 #define GEN11_BSD4_RING_BASE   0x1d4000
+#define XEHP_BSD5_RING_BASE    0x1e0000
+#define XEHP_BSD6_RING_BASE    0x1e4000
+#define XEHP_BSD7_RING_BASE    0x1f0000
+#define XEHP_BSD8_RING_BASE    0x1f4000
 #define VEBOX_RING_BASE                0x1a000
 #define GEN11_VEBOX_RING_BASE          0x1c8000
 #define GEN11_VEBOX2_RING_BASE         0x1d8000
+#define XEHP_VEBOX3_RING_BASE          0x1e8000
+#define XEHP_VEBOX4_RING_BASE          0x1f8000
 #define BLT_RING_BASE          0x22000
 #define RING_TAIL(base)                _MMIO((base) + 0x30)
 #define RING_HEAD(base)                _MMIO((base) + 0x34)
@@ -2563,7 +2577,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   ARB_MODE_BWGTLB_DISABLE (1 << 9)
 #define   ARB_MODE_SWIZZLE_BDW (1 << 1)
 #define RENDER_HWS_PGA_GEN7    _MMIO(0x04080)
-#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id)
+
+#define _RING_FAULT_REG_RCS        0x4094
+#define _RING_FAULT_REG_VCS        0x4194
+#define _RING_FAULT_REG_BCS        0x4294
+#define _RING_FAULT_REG_VECS       0x4394
+#define RING_FAULT_REG(engine)     _MMIO(_PICK((engine)->class, \
+                                              _RING_FAULT_REG_RCS, \
+                                              _RING_FAULT_REG_VCS, \
+                                              _RING_FAULT_REG_VECS, \
+                                              _RING_FAULT_REG_BCS))
 #define GEN8_RING_FAULT_REG    _MMIO(0x4094)
 #define GEN12_RING_FAULT_REG   _MMIO(0xcec4)
 #define   GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
@@ -2663,6 +2686,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define GEN12_SC_INSTDONE_EXTRA2       _MMIO(0x7108)
 #define GEN7_SAMPLER_INSTDONE  _MMIO(0xe160)
 #define GEN7_ROW_INSTDONE      _MMIO(0xe164)
+#define MCFG_MCR_SELECTOR              _MMIO(0xfd0)
+#define SF_MCR_SELECTOR                        _MMIO(0xfd8)
 #define GEN8_MCR_SELECTOR              _MMIO(0xfdc)
 #define   GEN8_MCR_SLICE(slice)                (((slice) & 3) << 26)
 #define   GEN8_MCR_SLICE_MASK          GEN8_MCR_SLICE(3)
@@ -3090,6 +3115,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define        GEN10_MIRROR_FUSE3              _MMIO(0x9118)
 #define GEN10_L3BANK_PAIR_COUNT     4
 #define GEN10_L3BANK_MASK   0x0F
+/* on Xe_HP the same fuses indicates mslices instead of L3 banks */
+#define GEN12_MAX_MSLICES 4
+#define GEN12_MEML3_EN_MASK 0x0F
 
 #define GEN8_EU_DISABLE0               _MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK         0xffffff
@@ -3124,6 +3152,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 
 #define GEN12_GT_DSS_ENABLE _MMIO(0x913C)
 
+#define XEHP_EU_ENABLE                 _MMIO(0x9134)
+#define XEHP_EU_ENA_MASK               0xFF
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL    _MMIO(0x12050)
 #define   GEN6_BSD_SLEEP_MSG_DISABLE   (1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
@@ -4077,6 +4108,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define BXT_GT_PERF_STATUS      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
 #define GEN6_RP_STATE_LIMITS   _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
 #define GEN6_RP_STATE_CAP      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
+#define   RP0_CAP_MASK         REG_GENMASK(7, 0)
+#define   RP1_CAP_MASK         REG_GENMASK(15, 8)
+#define   RPN_CAP_MASK         REG_GENMASK(23, 16)
 #define BXT_RP_STATE_CAP        _MMIO(0x138170)
 #define GEN9_RP_STATE_LIMITS   _MMIO(0x138148)
 
@@ -4133,6 +4167,7 @@ enum {
        FAULT_AND_CONTINUE /* Unsupported */
 };
 
+#define CTX_GTT_ADDRESS_MASK GENMASK(31, 12)
 #define GEN8_CTX_VALID (1 << 0)
 #define GEN8_CTX_FORCE_PD_RESTORE (1 << 1)
 #define GEN8_CTX_FORCE_RESTORE (1 << 2)
@@ -4149,6 +4184,11 @@ enum {
 #define GEN11_ENGINE_INSTANCE_SHIFT 48
 #define GEN11_ENGINE_INSTANCE_WIDTH 6
 
+#define XEHP_SW_CTX_ID_SHIFT 39
+#define XEHP_SW_CTX_ID_WIDTH 16
+#define XEHP_SW_COUNTER_SHIFT 58
+#define XEHP_SW_COUNTER_WIDTH 6
+
 #define CHV_CLK_CTL1                   _MMIO(0x101100)
 #define VLV_CLK_CTL2                   _MMIO(0x101104)
 #define   CLK_CTL2_CZCOUNT_30NS_SHIFT  28
@@ -8067,7 +8107,10 @@ enum {
 #define GEN11_BCS_RSVD_INTR_MASK       _MMIO(0x1900a0)
 #define GEN11_VCS0_VCS1_INTR_MASK      _MMIO(0x1900a8)
 #define GEN11_VCS2_VCS3_INTR_MASK      _MMIO(0x1900ac)
+#define GEN12_VCS4_VCS5_INTR_MASK      _MMIO(0x1900b0)
+#define GEN12_VCS6_VCS7_INTR_MASK      _MMIO(0x1900b4)
 #define GEN11_VECS0_VECS1_INTR_MASK    _MMIO(0x1900d0)
+#define GEN12_VECS2_VECS3_INTR_MASK    _MMIO(0x1900d4)
 #define GEN11_GUC_SG_INTR_MASK         _MMIO(0x1900e8)
 #define GEN11_GPM_WGBOXPERF_INTR_MASK  _MMIO(0x1900ec)
 #define GEN11_CRYPTO_RSVD_INTR_MASK    _MMIO(0x1900f0)
@@ -9193,6 +9236,8 @@ enum {
 #define   GEN9_FREQUENCY(x)                    ((x) << 23)
 #define   GEN6_OFFSET(x)                       ((x) << 19)
 #define   GEN6_AGGRESSIVE_TURBO                        (0 << 15)
+#define   GEN9_SW_REQ_UNSLICE_RATIO_SHIFT      23
+
 #define GEN6_RC_VIDEO_FREQ                     _MMIO(0xA00C)
 #define GEN6_RC_CONTROL                                _MMIO(0xA090)
 #define   GEN6_RC_CTL_RC6pp_ENABLE             (1 << 16)
@@ -12279,6 +12324,7 @@ enum skl_power_gate {
 
 /* MOCS (Memory Object Control State) registers */
 #define GEN9_LNCFCMOCS(i)      _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
+#define GEN9_LNCFCMOCS_REG_COUNT       32
 
 #define __GEN9_RCS0_MOCS0      0xc800
 #define GEN9_GFX_MOCS(i)       _MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)