Merge tag 'gvt-gt-next-2021-01-18' of https://github.com/intel/gvt-linux into drm...

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / gvt / handlers.c

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 920ff2c..6eeaeec 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -3121,9 +3121,10 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
        MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
        MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
        MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
-       MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS,
-               NULL, gen9_trtte_write);
-       MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write);
+       MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
+                NULL, gen9_trtte_write);
+       MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
+                NULL, gen9_trtt_chicken_write);
 
        MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
 
@@ -3672,3 +3673,39 @@ default_rw:
                intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) :
                intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes);
 }
+
+void intel_gvt_restore_fence(struct intel_gvt *gvt)
+{
+       struct intel_vgpu *vgpu;
+       int i, id;
+
+       idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) {
+               mmio_hw_access_pre(gvt->gt);
+               for (i = 0; i < vgpu_fence_sz(vgpu); i++)
+                       intel_vgpu_write_fence(vgpu, i, vgpu_vreg64(vgpu, fence_num_to_offset(i)));
+               mmio_hw_access_post(gvt->gt);
+       }
+}
+
+static int mmio_pm_restore_handler(struct intel_gvt *gvt, u32 offset, void *data)
+{
+       struct intel_vgpu *vgpu = data;
+       struct drm_i915_private *dev_priv = gvt->gt->i915;
+
+       if (gvt->mmio.mmio_attribute[offset >> 2] & F_PM_SAVE)
+               intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset));
+
+       return 0;
+}
+
+void intel_gvt_restore_mmio(struct intel_gvt *gvt)
+{
+       struct intel_vgpu *vgpu;
+       int id;
+
+       idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) {
+               mmio_hw_access_pre(gvt->gt);
+               intel_gvt_for_each_tracked_mmio(gvt, mmio_pm_restore_handler, vgpu);
+               mmio_hw_access_post(gvt->gt);
+       }
+}