Merge tag 'drm-intel-fixes-2020-10-29' into gvt-fixes

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / gvt / handlers.c

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index beafc5e..6a02653 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1921,7 +1921,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
        struct drm_i915_private *dev_priv = gvt->gt->i915;
        int ret;
 
-       MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL,
+       MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
                intel_vgpu_reg_imr_handler);
 
        MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
@@ -1929,7 +1929,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
        MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
        MMIO_D(SDEISR, D_ALL);
 
-       MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL);
+       MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
+
 
        MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
                gamw_echo_dev_rw_ia_write);
@@ -1956,11 +1957,11 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
        MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
        MMIO_D(GEN7_CXT_SIZE, D_ALL);
 
-       MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
-       MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
-       MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
-       MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL);
-       MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
+       MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
+       MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
+       MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
+       MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
+       MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
 
        /* RING MODE */
 #define RING_REG(base) _MMIO((base) + 0x29c)
@@ -2715,7 +2716,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
        MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
 
        MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
-       MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL);
+       MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
        MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
        MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
        MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
@@ -2800,7 +2801,7 @@ static int init_bdw_mmio_info(struct intel_gvt *gvt)
        MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
                intel_vgpu_reg_master_irq_handler);
 
-       MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS,
+       MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
                mmio_read_from_hw, NULL);
 
 #define RING_REG(base) _MMIO((base) + 0xd0)
@@ -2814,7 +2815,7 @@ static int init_bdw_mmio_info(struct intel_gvt *gvt)
 #undef RING_REG
 
 #define RING_REG(base) _MMIO((base) + 0x234)
-       MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
+       MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
                NULL, NULL);
 #undef RING_REG
 
@@ -2849,7 +2850,7 @@ static int init_bdw_mmio_info(struct intel_gvt *gvt)
        MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
 #undef RING_REG
 
-       MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
+       MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
 
        MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
 
@@ -2950,7 +2951,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
        MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
        MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
        MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
-       MMIO_DH(MMCD_MISC_CTRL, D_SKL_PLUS, NULL, NULL);
+       MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
        MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
        MMIO_D(DC_STATE_EN, D_SKL_PLUS);
        MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
@@ -3166,7 +3167,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
        MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
                 NULL, NULL);
 
-       MMIO_D(GAMT_CHKN_BIT_REG, D_KBL | D_CFL);
+       MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
        MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS);
 
        return 0;
@@ -3388,7 +3389,10 @@ void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
        gvt->mmio.mmio_attribute = NULL;
 }
 
-/* Special MMIO blocks. */
+/* Special MMIO blocks. registers in MMIO block ranges should not be command
+ * accessible (should have no F_CMD_ACCESS flag).
+ * otherwise, need to update cmd_reg_handler in cmd_parser.c
+ */
 static struct gvt_mmio_block mmio_blocks[] = {
        {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
        {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},