Merge tag 'drm-next-2021-08-31-1' of git://anongit.freedesktop.org/drm/drm

[linux-2.6-microblaze.git] / drivers / gpu / drm / i915 / display / intel_dp.c

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 862c1df..04175f3 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -222,29 +222,6 @@ bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
                 encoder->port != PORT_A);
 }
 
-static int cnl_max_source_rate(struct intel_dp *intel_dp)
-{
-       struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-       struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
-       enum port port = dig_port->base.port;
-
-       u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
-
-       /* Low voltage SKUs are limited to max of 5.4G */
-       if (voltage == VOLTAGE_INFO_0_85V)
-               return 540000;
-
-       /* For this SKU 8.1G is supported in all ports */
-       if (IS_CNL_WITH_PORT_F(dev_priv))
-               return 810000;
-
-       /* For other SKUs, max rate on ports A and D is 5.4G */
-       if (port == PORT_A || port == PORT_D)
-               return 540000;
-
-       return 810000;
-}
-
 static int icl_max_source_rate(struct intel_dp *intel_dp)
 {
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -270,7 +247,7 @@ static void
 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {
        /* The values must be in increasing order */
-       static const int cnl_rates[] = {
+       static const int icl_rates[] = {
                162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
        };
        static const int bxt_rates[] = {
@@ -295,12 +272,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
        drm_WARN_ON(&dev_priv->drm,
                    intel_dp->source_rates || intel_dp->num_source_rates);
 
-       if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
-               source_rates = cnl_rates;
-               size = ARRAY_SIZE(cnl_rates);
-               if (DISPLAY_VER(dev_priv) == 10)
-                       max_rate = cnl_max_source_rate(intel_dp);
-               else if (IS_JSL_EHL(dev_priv))
+       if (DISPLAY_VER(dev_priv) >= 11) {
+               source_rates = icl_rates;
+               size = ARRAY_SIZE(icl_rates);
+               if (IS_JSL_EHL(dev_priv))
                        max_rate = ehl_max_source_rate(intel_dp);
                else
                        max_rate = icl_max_source_rate(intel_dp);
@@ -1274,6 +1249,23 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
                                                               pipe_config->pipe_bpp);
                pipe_config->dsc.slice_count = dsc_dp_slice_count;
        }
+
+       /* As of today we support DSC for only RGB */
+       if (intel_dp->force_dsc_bpp) {
+               if (intel_dp->force_dsc_bpp >= 8 &&
+                   intel_dp->force_dsc_bpp < pipe_bpp) {
+                       drm_dbg_kms(&dev_priv->drm,
+                                   "DSC BPP forced to %d",
+                                   intel_dp->force_dsc_bpp);
+                       pipe_config->dsc.compressed_bpp =
+                                               intel_dp->force_dsc_bpp;
+               } else {
+                       drm_dbg_kms(&dev_priv->drm,
+                                   "Invalid DSC BPP %d",
+                                   intel_dp->force_dsc_bpp);
+               }
+       }
+
        /*
         * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
         * is greater than the maximum Cdclock and if slice count is even
@@ -3031,9 +3023,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
                       struct intel_crtc_state *crtc_state,
                       unsigned int type)
 {
-       if (encoder->type != INTEL_OUTPUT_DDI)
-               return;
-
        switch (type) {
        case DP_SDP_VSC:
                intel_read_dp_vsc_sdp(encoder, crtc_state,
@@ -3342,6 +3331,9 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
 
        intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
 
+       drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
+                         intel_dp->train_set, crtc_state->lane_count);
+
        drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
                                    link_status[DP_DPCD_REV]);
 }
@@ -4736,7 +4728,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
                                    int refresh_rate)
 {
        struct intel_dp *intel_dp = dev_priv->drrs.dp;
-       struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
 
        if (refresh_rate <= 0) {
@@ -4750,7 +4742,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
                return;
        }
 
-       if (!intel_crtc) {
+       if (!crtc) {
                drm_dbg_kms(&dev_priv->drm,
                            "DRRS: intel_crtc not initialized\n");
                return;
@@ -5233,7 +5225,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
        }
 
        intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
-       intel_connector->panel.backlight.power = intel_pps_backlight_power;
+       if (!(dev_priv->quirks & QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))
+               intel_connector->panel.backlight.power = intel_pps_backlight_power;
        intel_panel_setup_backlight(connector, pipe);
 
        if (fixed_mode) {