drm/etnaviv: replace MMU flush marker with flush sequence

[linux-2.6-microblaze.git] / drivers / gpu / drm / etnaviv / etnaviv_buffer.c

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
index 6400a88..a3cdb20 100644 (file)
--- a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
@@ -315,6 +315,8 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
        u32 return_target, return_dwords;
        u32 link_target, link_dwords;
        bool switch_context = gpu->exec_state != exec_state;
+       unsigned int new_flush_seq = READ_ONCE(gpu->mmu->flush_seq);
+       bool need_flush = gpu->flush_seq != new_flush_seq;
 
        lockdep_assert_held(&gpu->lock);
 
@@ -329,14 +331,14 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
         * need to append a mmu flush load state, followed by a new
         * link to this buffer - a total of four additional words.
         */
-       if (gpu->mmu->need_flush || switch_context) {
+       if (need_flush || switch_context) {
                u32 target, extra_dwords;
 
                /* link command */
                extra_dwords = 1;
 
                /* flush command */
-               if (gpu->mmu->need_flush) {
+               if (need_flush) {
                        if (gpu->mmu->version == ETNAVIV_IOMMU_V1)
                                extra_dwords += 1;
                        else
@@ -349,7 +351,7 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
 
                target = etnaviv_buffer_reserve(gpu, buffer, extra_dwords);
 
-               if (gpu->mmu->need_flush) {
+               if (need_flush) {
                        /* Add the MMU flush */
                        if (gpu->mmu->version == ETNAVIV_IOMMU_V1) {
                                CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_MMU,
@@ -369,7 +371,7 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
                                        SYNC_RECIPIENT_PE);
                        }
 
-                       gpu->mmu->need_flush = false;
+                       gpu->flush_seq = new_flush_seq;
                }
 
                if (switch_context) {