drm/amd/display: Multi-display underflow observed
[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / display / dc / dcn20 / dcn20_hwseq.c
index 31a4771..cb822df 100644 (file)
@@ -1586,7 +1586,10 @@ static void dcn20_program_pipe(
                        && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
                hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
 
-       if (pipe_ctx->update_flags.bits.global_sync) {
+       /* Only update TG on top pipe */
+       if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe
+                       && !pipe_ctx->prev_odm_pipe) {
+
                pipe_ctx->stream_res.tg->funcs->program_global_sync(
                                pipe_ctx->stream_res.tg,
                                pipe_ctx->pipe_dlg_param.vready_offset,
@@ -1594,8 +1597,11 @@ static void dcn20_program_pipe(
                                pipe_ctx->pipe_dlg_param.vupdate_offset,
                                pipe_ctx->pipe_dlg_param.vupdate_width);
 
+               pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
+               pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
+
                pipe_ctx->stream_res.tg->funcs->set_vtg_params(
-                               pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);
+                               pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
 
                if (hws->funcs.setup_vupdate_interrupt)
                        hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
@@ -2570,4 +2576,4 @@ void dcn20_set_disp_pattern_generator(const struct dc *dc,
 {
        pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
                        color_space, color_depth, solid_color, width, height, offset);
-}
\ No newline at end of file
+}