Merge tag 'drm-next-2020-12-24' of git://anongit.freedesktop.org/drm/drm

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index fc9bb94..5f4805e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1647,7 +1647,7 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
        }
 
        /* No CPG in Arcturus */
-       if (adev->asic_type != CHIP_ARCTURUS) {
+       if (adev->gfx.num_gfx_rings) {
                r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name);
                if (r)
                        return r;
@@ -2633,7 +2633,14 @@ static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
                                               bool enable)
 {
-       u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
+       u32 tmp;
+
+       /* don't toggle interrupts that are only applicable
+        * to me0 pipe0 on AISCs that have me0 removed */
+       if (!adev->gfx.num_gfx_rings)
+               return;
+
+       tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
 
        tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
        tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
@@ -3822,7 +3829,7 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
                gfx_v9_0_enable_gui_idle_interrupt(adev, false);
 
        if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
-               if (adev->asic_type != CHIP_ARCTURUS) {
+               if (adev->gfx.num_gfx_rings) {
                        /* legacy firmware loading */
                        r = gfx_v9_0_cp_gfx_load_microcode(adev);
                        if (r)
@@ -3838,7 +3845,7 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
        if (r)
                return r;
 
-       if (adev->asic_type != CHIP_ARCTURUS) {
+       if (adev->gfx.num_gfx_rings) {
                r = gfx_v9_0_cp_gfx_resume(adev);
                if (r)
                        return r;
@@ -3848,7 +3855,7 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
        if (r)
                return r;
 
-       if (adev->asic_type != CHIP_ARCTURUS) {
+       if (adev->gfx.num_gfx_rings) {
                ring = &adev->gfx.gfx_ring[0];
                r = amdgpu_ring_test_helper(ring);
                if (r)
@@ -3884,7 +3891,7 @@ static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev)
 
 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
 {
-       if (adev->asic_type != CHIP_ARCTURUS)
+       if (adev->gfx.num_gfx_rings)
                gfx_v9_0_cp_gfx_enable(adev, enable);
        gfx_v9_0_cp_compute_enable(adev, enable);
 }
@@ -4025,7 +4032,7 @@ static int gfx_v9_0_soft_reset(void *handle)
                /* stop the rlc */
                adev->gfx.rlc.funcs->stop(adev);
 
-               if (adev->asic_type != CHIP_ARCTURUS)
+               if (adev->gfx.num_gfx_rings)
                        /* Disable GFX parsing/prefetching */
                        gfx_v9_0_cp_gfx_enable(adev, false);