drm/amdgpu: implement more ib pools (v2)

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_vm_sdma.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index 19b7f80..fbd451f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -58,29 +58,23 @@ static int amdgpu_vm_sdma_map_table(struct amdgpu_bo *table)
  * Negativ errno, 0 for success.
  */
 static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p,
-                                 void *owner, struct dma_fence *exclusive)
+                                 struct dma_resv *resv,
+                                 enum amdgpu_sync_mode sync_mode)
 {
-       struct amdgpu_bo *root = p->vm->root.base.bo;
        unsigned int ndw = AMDGPU_VM_SDMA_MIN_NUM_DW;
        int r;
 
-       r = amdgpu_job_alloc_with_ib(p->adev, ndw * 4, &p->job);
+       r = amdgpu_job_alloc_with_ib(p->adev, ndw * 4,
+                       p->direct ? AMDGPU_IB_POOL_VM : AMDGPU_IB_POOL_NORMAL, &p->job);
        if (r)
                return r;
 
        p->num_dw_left = ndw;
 
-       /* Wait for moves to be completed */
-       r = amdgpu_sync_fence(&p->job->sync, exclusive, false);
-       if (r)
-               return r;
-
-       /* Don't wait for any submissions during page fault handling */
-       if (p->direct)
+       if (!resv)
                return 0;
 
-       return amdgpu_sync_resv(p->adev, &p->job->sync, root->tbo.base.resv,
-                               owner, false);
+       return amdgpu_sync_resv(p->adev, &p->job->sync, resv, sync_mode, p->vm);
 }
 
 /**
@@ -111,12 +105,13 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p,
        if (r)
                goto error;
 
-       tmp = dma_fence_get(f);
-       if (p->direct)
+       if (p->direct) {
+               tmp = dma_fence_get(f);
                swap(p->vm->last_direct, tmp);
-       else
-               swap(p->vm->last_delayed, tmp);
-       dma_fence_put(tmp);
+               dma_fence_put(tmp);
+       } else {
+               dma_resv_add_shared_fence(p->vm->root.base.bo->tbo.base.resv, f);
+       }
 
        if (fence && !p->direct)
                swap(*fence, f);
@@ -147,7 +142,7 @@ static void amdgpu_vm_sdma_copy_ptes(struct amdgpu_vm_update_params *p,
 
        src += p->num_dw_left * 4;
 
-       pe += amdgpu_bo_gpu_offset(bo);
+       pe += amdgpu_gmc_sign_extend(bo->tbo.offset);
        trace_amdgpu_vm_copy_ptes(pe, src, count, p->direct);
 
        amdgpu_vm_copy_pte(p->adev, ib, pe, src, count);
@@ -174,7 +169,7 @@ static void amdgpu_vm_sdma_set_ptes(struct amdgpu_vm_update_params *p,
 {
        struct amdgpu_ib *ib = p->job->ibs;
 
-       pe += amdgpu_bo_gpu_offset(bo);
+       pe += amdgpu_gmc_sign_extend(bo->tbo.offset);
        trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->direct);
        if (count < 3) {
                amdgpu_vm_write_pte(p->adev, ib, pe, addr | flags,
@@ -208,6 +203,11 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,
        uint64_t *pte;
        int r;
 
+       /* Wait for PD/PT moves to be completed */
+       r = amdgpu_sync_fence(&p->job->sync, bo->tbo.moving, false);
+       if (r)
+               return r;
+
        do {
                ndw = p->num_dw_left;
                ndw -= p->job->ibs->length_dw;
@@ -224,7 +224,8 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,
                        ndw = max(ndw, AMDGPU_VM_SDMA_MIN_NUM_DW);
                        ndw = min(ndw, AMDGPU_VM_SDMA_MAX_NUM_DW);
 
-                       r = amdgpu_job_alloc_with_ib(p->adev, ndw * 4, &p->job);
+                       r = amdgpu_job_alloc_with_ib(p->adev, ndw * 4,
+                                       p->direct ? AMDGPU_IB_POOL_VM : AMDGPU_IB_POOL_NORMAL, &p->job);
                        if (r)
                                return r;