Merge drm/drm-next into drm-misc-next

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_drv.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index f359ffb..8b30915 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -32,7 +32,6 @@
 #include <drm/drm_pciids.h>
 #include <linux/console.h>
 #include <linux/module.h>
-#include <linux/pci.h>
 #include <linux/pm_runtime.h>
 #include <linux/vga_switcheroo.h>
 #include <drm/drm_probe_helper.h>
@@ -148,7 +147,7 @@ int amdgpu_async_gfx_ring = 1;
 int amdgpu_mcbp = 0;
 int amdgpu_discovery = -1;
 int amdgpu_mes = 0;
-int amdgpu_noretry;
+int amdgpu_noretry = -1;
 int amdgpu_force_asic_type = -1;
 int amdgpu_tmz = 0;
 int amdgpu_reset_method = -1; /* auto */
@@ -597,8 +596,13 @@ MODULE_PARM_DESC(mes,
        "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
 module_param_named(mes, amdgpu_mes, int, 0444);
 
+/**
+ * DOC: noretry (int)
+ * Disable retry faults in the GPU memory controller.
+ * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
+ */
 MODULE_PARM_DESC(noretry,
-       "Disable retry faults (0 = retry enabled (default), 1 = retry disabled)");
+       "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
 module_param_named(noretry, amdgpu_noretry, int, 0644);
 
 /**
@@ -1062,6 +1066,7 @@ static const struct pci_device_id pciidlist[] = {
        {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
        {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
        {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
+       {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
        {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
        /* Navi14 */
        {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
@@ -1073,8 +1078,16 @@ static const struct pci_device_id pciidlist[] = {
        {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
 
        /* Navi12 */
-       {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT},
-       {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT},
+       {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
+       {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
+
+       /* Sienna_Cichlid */
+       {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
+       {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
+       {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
+       {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
+       {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
+       {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
 
        {0, 0, 0}
 };
@@ -1102,6 +1115,16 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
                return -ENODEV;
        }
 
+       /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
+        * however, SME requires an indirect IOMMU mapping because the encryption
+        * bit is beyond the DMA mask of the chip.
+        */
+       if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
+               dev_info(&pdev->dev,
+                        "SME is not compatible with RAVEN\n");
+               return -ENOTSUPP;
+       }
+
 #ifdef CONFIG_DRM_AMDGPU_SI
        if (!amdgpu_si_support) {
                switch (flags & AMD_ASIC_MASK) {
@@ -1308,7 +1331,7 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev)
                if (amdgpu_is_atpx_hybrid()) {
                        pci_ignore_hotplug(pdev);
                } else {
-                       pci_save_state(pdev);
+                       amdgpu_device_cache_pci_state(pdev);
                        pci_disable_device(pdev);
                        pci_ignore_hotplug(pdev);
                        pci_set_power_state(pdev, PCI_D3cold);
@@ -1341,7 +1364,7 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
                        pci_set_master(pdev);
                } else {
                        pci_set_power_state(pdev, PCI_D0);
-                       pci_restore_state(pdev);
+                       amdgpu_device_load_pci_state(pdev);
                        ret = pci_enable_device(pdev);
                        if (ret)
                                return ret;
@@ -1514,6 +1537,13 @@ static struct drm_driver kms_driver = {
        .patchlevel = KMS_DRIVER_PATCHLEVEL,
 };
 
+static struct pci_error_handlers amdgpu_pci_err_handler = {
+       .error_detected = amdgpu_pci_error_detected,
+       .mmio_enabled   = amdgpu_pci_mmio_enabled,
+       .slot_reset     = amdgpu_pci_slot_reset,
+       .resume         = amdgpu_pci_resume,
+};
+
 static struct pci_driver amdgpu_kms_pci_driver = {
        .name = DRIVER_NAME,
        .id_table = pciidlist,
@@ -1521,6 +1551,7 @@ static struct pci_driver amdgpu_kms_pci_driver = {
        .remove = amdgpu_pci_remove,
        .shutdown = amdgpu_pci_shutdown,
        .driver.pm = &amdgpu_pm_ops,
+       .err_handler = &amdgpu_pci_err_handler,
 };
 
 static int __init amdgpu_init(void)