Merge tag 'dt-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_amdkfd.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index f9c01bd..3003ee1 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -21,6 +21,7 @@
  */
 
 #include "amdgpu_amdkfd.h"
+#include "amd_pcie.h"
 #include "amd_shared.h"
 
 #include "amdgpu.h"
@@ -553,6 +554,88 @@ uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *s
        return  (uint8_t)ret;
 }
 
+int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct kgd_dev *dst, struct kgd_dev *src, bool is_min)
+{
+       struct amdgpu_device *adev = (struct amdgpu_device *)dst, *peer_adev;
+       int num_links;
+
+       if (adev->asic_type != CHIP_ALDEBARAN)
+               return 0;
+
+       if (src)
+               peer_adev = (struct amdgpu_device *)src;
+
+       /* num links returns 0 for indirect peers since indirect route is unknown. */
+       num_links = is_min ? 1 : amdgpu_xgmi_get_num_links(adev, peer_adev);
+       if (num_links < 0) {
+               DRM_ERROR("amdgpu: failed to get xgmi num links between node %d and %d. ret = %d\n",
+                       adev->gmc.xgmi.physical_node_id,
+                       peer_adev->gmc.xgmi.physical_node_id, num_links);
+               num_links = 0;
+       }
+
+       /* Aldebaran xGMI DPM is defeatured so assume x16 x 25Gbps for bandwidth. */
+       return (num_links * 16 * 25000)/BITS_PER_BYTE;
+}
+
+int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct kgd_dev *dev, bool is_min)
+{
+       struct amdgpu_device *adev = (struct amdgpu_device *)dev;
+       int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) :
+                                                       fls(adev->pm.pcie_mlw_mask)) - 1;
+       int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask &
+                                               CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) :
+                                       fls(adev->pm.pcie_gen_mask &
+                                               CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1;
+       uint32_t num_lanes_mask = 1 << num_lanes_shift;
+       uint32_t gen_speed_mask = 1 << gen_speed_shift;
+       int num_lanes_factor = 0, gen_speed_mbits_factor = 0;
+
+       switch (num_lanes_mask) {
+       case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
+               num_lanes_factor = 1;
+               break;
+       case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
+               num_lanes_factor = 2;
+               break;
+       case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
+               num_lanes_factor = 4;
+               break;
+       case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
+               num_lanes_factor = 8;
+               break;
+       case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
+               num_lanes_factor = 12;
+               break;
+       case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
+               num_lanes_factor = 16;
+               break;
+       case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
+               num_lanes_factor = 32;
+               break;
+       }
+
+       switch (gen_speed_mask) {
+       case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1:
+               gen_speed_mbits_factor = 2500;
+               break;
+       case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2:
+               gen_speed_mbits_factor = 5000;
+               break;
+       case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3:
+               gen_speed_mbits_factor = 8000;
+               break;
+       case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4:
+               gen_speed_mbits_factor = 16000;
+               break;
+       case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5:
+               gen_speed_mbits_factor = 32000;
+               break;
+       }
+
+       return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE;
+}
+
 uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
@@ -631,7 +714,6 @@ int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
        ret = dma_fence_wait(f, false);
 
 err_ib_sched:
-       dma_fence_put(f);
        amdgpu_job_free(job);
 err:
        return ret;