Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

[linux-2.6-microblaze.git] / drivers / clk / sunxi-ng / ccu-sun8i-r.c

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
index b5be11e..4646fdc 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
@@ -17,10 +17,13 @@
 
 #include "ccu-sun8i-r.h"
 
-static const char * const ar100_parents[] = { "osc32k", "osc24M",
-                                            "pll-periph0", "iosc" };
-static const char * const a83t_ar100_parents[] = { "osc16M-d512", "osc24M",
-                                                  "pll-periph0", "iosc" };
+static const struct clk_parent_data ar100_parents[] = {
+       { .fw_name = "losc" },
+       { .fw_name = "hosc" },
+       { .fw_name = "pll-periph" },
+       { .fw_name = "iosc" },
+};
+
 static const struct ccu_mux_var_prediv ar100_predivs[] = {
        { .index = 2, .shift = 8, .width = 5 },
 };
@@ -39,64 +42,49 @@ static struct ccu_div ar100_clk = {
        .common         = {
                .reg            = 0x00,
                .features       = CCU_FEATURE_VARIABLE_PREDIV,
-               .hw.init        = CLK_HW_INIT_PARENTS("ar100",
-                                                     ar100_parents,
-                                                     &ccu_div_ops,
-                                                     0),
-       },
-};
-
-static struct ccu_div a83t_ar100_clk = {
-       .div            = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
-
-       .mux            = {
-               .shift  = 16,
-               .width  = 2,
-
-               .var_predivs    = ar100_predivs,
-               .n_var_predivs  = ARRAY_SIZE(ar100_predivs),
-       },
-
-       .common         = {
-               .reg            = 0x00,
-               .features       = CCU_FEATURE_VARIABLE_PREDIV,
-               .hw.init        = CLK_HW_INIT_PARENTS("ar100",
-                                                     a83t_ar100_parents,
-                                                     &ccu_div_ops,
-                                                     0),
+               .hw.init        = CLK_HW_INIT_PARENTS_DATA("ar100",
+                                                          ar100_parents,
+                                                          &ccu_div_ops,
+                                                          0),
        },
 };
 
-static CLK_FIXED_FACTOR(ahb0_clk, "ahb0", "ar100", 1, 1, 0);
+static CLK_FIXED_FACTOR_HW(ahb0_clk, "ahb0", &ar100_clk.common.hw, 1, 1, 0);
 
 static struct ccu_div apb0_clk = {
        .div            = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
 
        .common         = {
                .reg            = 0x0c,
-               .hw.init        = CLK_HW_INIT("apb0",
-                                             "ahb0",
-                                             &ccu_div_ops,
-                                             0),
+               .hw.init        = CLK_HW_INIT_HW("apb0",
+                                                &ahb0_clk.hw,
+                                                &ccu_div_ops,
+                                                0),
        },
 };
 
 static SUNXI_CCU_M(a83t_apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0);
 
-static SUNXI_CCU_GATE(apb0_pio_clk,    "apb0-pio",     "apb0",
-                     0x28, BIT(0), 0);
-static SUNXI_CCU_GATE(apb0_ir_clk,     "apb0-ir",      "apb0",
-                     0x28, BIT(1), 0);
-static SUNXI_CCU_GATE(apb0_timer_clk,  "apb0-timer",   "apb0",
-                     0x28, BIT(2), 0);
-static SUNXI_CCU_GATE(apb0_rsb_clk,    "apb0-rsb",     "apb0",
-                     0x28, BIT(3), 0);
-static SUNXI_CCU_GATE(apb0_uart_clk,   "apb0-uart",    "apb0",
-                     0x28, BIT(4), 0);
-static SUNXI_CCU_GATE(apb0_i2c_clk,    "apb0-i2c",     "apb0",
-                     0x28, BIT(6), 0);
-static SUNXI_CCU_GATE(apb0_twd_clk,    "apb0-twd",     "apb0",
-                     0x28, BIT(7), 0);
+/*
+ * Define the parent as an array that can be reused to save space
+ * instead of having compound literals for each gate. Also have it
+ * non-const so we can change it on the A83T.
+ */
+static const struct clk_hw *apb0_gate_parent[] = { &apb0_clk.common.hw };
+static SUNXI_CCU_GATE_HWS(apb0_pio_clk,                "apb0-pio",
+                         apb0_gate_parent, 0x28, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(apb0_ir_clk,         "apb0-ir",
+                         apb0_gate_parent, 0x28, BIT(1), 0);
+static SUNXI_CCU_GATE_HWS(apb0_timer_clk,      "apb0-timer",
+                         apb0_gate_parent, 0x28, BIT(2), 0);
+static SUNXI_CCU_GATE_HWS(apb0_rsb_clk,                "apb0-rsb",
+                         apb0_gate_parent, 0x28, BIT(3), 0);
+static SUNXI_CCU_GATE_HWS(apb0_uart_clk,       "apb0-uart",
+                         apb0_gate_parent, 0x28, BIT(4), 0);
+static SUNXI_CCU_GATE_HWS(apb0_i2c_clk,                "apb0-i2c",
+                         apb0_gate_parent, 0x28, BIT(6), 0);
+static SUNXI_CCU_GATE_HWS(apb0_twd_clk,                "apb0-twd",
+                         apb0_gate_parent, 0x28, BIT(7), 0);
 
 static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
@@ -107,7 +95,10 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
                                  BIT(31),      /* gate */
                                  0);
 
-static const char *const a83t_r_mod0_parents[] = { "osc16M", "osc24M" };
+static const struct clk_parent_data a83t_r_mod0_parents[] = {
+       { .fw_name = "iosc" },
+       { .fw_name = "hosc" },
+};
 static const struct ccu_mux_fixed_prediv a83t_ir_predivs[] = {
        { .index = 0, .div = 16 },
 };
@@ -127,15 +118,15 @@ static struct ccu_mp a83t_ir_clk = {
        .common         = {
                .reg            = 0x54,
                .features       = CCU_FEATURE_VARIABLE_PREDIV,
-               .hw.init        = CLK_HW_INIT_PARENTS("ir",
-                                                     a83t_r_mod0_parents,
-                                                     &ccu_mp_ops,
-                                                     0),
+               .hw.init        = CLK_HW_INIT_PARENTS_DATA("ir",
+                                                          a83t_r_mod0_parents,
+                                                          &ccu_mp_ops,
+                                                          0),
        },
 };
 
 static struct ccu_common *sun8i_a83t_r_ccu_clks[] = {
-       &a83t_ar100_clk.common,
+       &ar100_clk.common,
        &a83t_apb0_clk.common,
        &apb0_pio_clk.common,
        &apb0_ir_clk.common,
@@ -174,7 +165,7 @@ static struct ccu_common *sun50i_a64_r_ccu_clks[] = {
 
 static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = {
        .hws    = {
-               [CLK_AR100]             = &a83t_ar100_clk.common.hw,
+               [CLK_AR100]             = &ar100_clk.common.hw,
                [CLK_AHB0]              = &ahb0_clk.hw,
                [CLK_APB0]              = &a83t_apb0_clk.common.hw,
                [CLK_APB0_PIO]          = &apb0_pio_clk.common.hw,
@@ -291,6 +282,9 @@ static void __init sunxi_r_ccu_init(struct device_node *node,
 
 static void __init sun8i_a83t_r_ccu_setup(struct device_node *node)
 {
+       /* Fix apb0 bus gate parents here */
+       apb0_gate_parent[0] = &a83t_apb0_clk.common.hw;
+
        sunxi_r_ccu_init(node, &sun8i_a83t_r_ccu_desc);
 }
 CLK_OF_DECLARE(sun8i_a83t_r_ccu, "allwinner,sun8i-a83t-r-ccu",