Merge tag 'kvm-ppc-next-5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/paulu...

[linux-2.6-microblaze.git] / arch / powerpc / include / asm / reg.h

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 88e6c78..88fb884 100644 (file)
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -12,6 +12,7 @@
 #ifdef __KERNEL__
 
 #include <linux/stringify.h>
+#include <linux/const.h>
 #include <asm/cputable.h>
 #include <asm/asm-const.h>
 #include <asm/feature-fixups.h>
@@ -473,7 +474,8 @@
 #ifndef SPRN_LPID
 #define SPRN_LPID      0x13F   /* Logical Partition Identifier */
 #endif
-#define   LPID_RSVD    0x3ff           /* Reserved LPID for partn switching */
+#define   LPID_RSVD_POWER7     0x3ff   /* Reserved LPID for partn switching */
+#define   LPID_RSVD            0xfff   /* Reserved LPID for partn switching */
 #define        SPRN_HMER       0x150   /* Hypervisor maintenance exception reg */
 #define   HMER_DEBUG_TRIG      (1ul << (63 - 17)) /* Debug trigger */
 #define        SPRN_HMEER      0x151   /* Hyp maintenance exception enable reg */
@@ -876,7 +878,9 @@
 #define   MMCR0_FCHV   0x00000001UL /* freeze conditions in hypervisor mode */
 #define SPRN_MMCR1     798
 #define SPRN_MMCR2     785
+#define SPRN_MMCR3     754
 #define SPRN_UMMCR2    769
+#define SPRN_UMMCR3    738
 #define SPRN_MMCRA     0x312
 #define   MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */
 #define   MMCRA_SDAR_DCACHE_MISS 0x40000000UL
@@ -886,6 +890,7 @@
 #define   MMCRA_SLOT   0x07000000UL /* SLOT bits (37-39) */
 #define   MMCRA_SLOT_SHIFT     24
 #define   MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
+#define   MMCRA_BHRB_DISABLE  _UL(0x2000000000) // BHRB disable bit for ISA v3.1
 #define   POWER6_MMCRA_SDSYNC 0x0000080000000000ULL    /* SDAR/SIAR synced */
 #define   POWER6_MMCRA_SIHV   0x0000040000000000ULL
 #define   POWER6_MMCRA_SIPR   0x0000020000000000ULL
@@ -918,6 +923,10 @@
 #define   SIER_SIHV            0x1000000       /* Sampled MSR_HV */
 #define   SIER_SIAR_VALID      0x0400000       /* SIAR contents valid */
 #define   SIER_SDAR_VALID      0x0200000       /* SDAR contents valid */
+#define SPRN_SIER2     752
+#define SPRN_SIER3     753
+#define SPRN_USIER2    736
+#define SPRN_USIER3    737
 #define SPRN_SIAR      796
 #define SPRN_SDAR      797
 #define SPRN_TACR      888
@@ -1354,6 +1363,7 @@
 #define PVR_ARCH_206p  0x0f100003
 #define PVR_ARCH_207   0x0f000004
 #define PVR_ARCH_300   0x0f000005
+#define PVR_ARCH_31    0x0f000006
 
 /* Macros for setting and retrieving special purpose registers */
 #ifndef __ASSEMBLY__
@@ -1472,7 +1482,7 @@ static inline void update_power8_hid0(unsigned long hid0)
 {
        /*
         *  The HID0 update on Power8 should at the very least be
-        *  preceded by a a SYNC instruction followed by an ISYNC
+        *  preceded by a SYNC instruction followed by an ISYNC
         *  instruction
         */
        asm volatile("sync; mtspr %0,%1; isync":: "i"(SPRN_HID0), "r"(hid0));