arm64: entry: consolidate Cortex-A76 erratum 1463225 workaround

[linux-2.6-microblaze.git] / arch / arm64 / kernel / syscall.c

diff --git a/arch/arm64/kernel/syscall.c b/arch/arm64/kernel/syscall.c
index c2877c3..b9cf12b 100644 (file)
--- a/arch/arm64/kernel/syscall.c
+++ b/arch/arm64/kernel/syscall.c
@@ -65,35 +65,6 @@ static inline bool has_syscall_work(unsigned long flags)
 int syscall_trace_enter(struct pt_regs *regs);
 void syscall_trace_exit(struct pt_regs *regs);
 
-#ifdef CONFIG_ARM64_ERRATUM_1463225
-DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
-
-static void cortex_a76_erratum_1463225_svc_handler(void)
-{
-       u32 reg, val;
-
-       if (!unlikely(test_thread_flag(TIF_SINGLESTEP)))
-               return;
-
-       if (!unlikely(this_cpu_has_cap(ARM64_WORKAROUND_1463225)))
-               return;
-
-       __this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 1);
-       reg = read_sysreg(mdscr_el1);
-       val = reg | DBG_MDSCR_SS | DBG_MDSCR_KDE;
-       write_sysreg(val, mdscr_el1);
-       asm volatile("msr daifclr, #8");
-       isb();
-
-       /* We will have taken a single-step exception by this point */
-
-       write_sysreg(reg, mdscr_el1);
-       __this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 0);
-}
-#else
-static void cortex_a76_erratum_1463225_svc_handler(void) { }
-#endif /* CONFIG_ARM64_ERRATUM_1463225 */
-
 static void el0_svc_common(struct pt_regs *regs, int scno, int sc_nr,
                           const syscall_fn_t syscall_table[])
 {
@@ -120,7 +91,6 @@ static void el0_svc_common(struct pt_regs *regs, int scno, int sc_nr,
         * (Similarly for HVC and SMC elsewhere.)
         */
 
-       cortex_a76_erratum_1463225_svc_handler();
        local_daif_restore(DAIF_PROCCTX);
 
        if (flags & _TIF_MTE_ASYNC_FAULT) {