Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

[linux-2.6-microblaze.git] / arch / arm64 / include / asm / sysreg.h

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index f2e06e7..b268082 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -784,14 +784,13 @@
 #define ID_AA64PFR0_AMU                        0x1
 #define ID_AA64PFR0_SVE                        0x1
 #define ID_AA64PFR0_RAS_V1             0x1
+#define ID_AA64PFR0_RAS_V1P1           0x2
 #define ID_AA64PFR0_FP_NI              0xf
 #define ID_AA64PFR0_FP_SUPPORTED       0x0
 #define ID_AA64PFR0_ASIMD_NI           0xf
 #define ID_AA64PFR0_ASIMD_SUPPORTED    0x0
-#define ID_AA64PFR0_EL1_64BIT_ONLY     0x1
-#define ID_AA64PFR0_EL1_32BIT_64BIT    0x2
-#define ID_AA64PFR0_EL0_64BIT_ONLY     0x1
-#define ID_AA64PFR0_EL0_32BIT_64BIT    0x2
+#define ID_AA64PFR0_ELx_64BIT_ONLY     0x1
+#define ID_AA64PFR0_ELx_32BIT_64BIT    0x2
 
 /* id_aa64pfr1 */
 #define ID_AA64PFR1_MPAMFRAC_SHIFT     16
@@ -847,6 +846,9 @@
 #define ID_AA64MMFR0_ASID_SHIFT                4
 #define ID_AA64MMFR0_PARANGE_SHIFT     0
 
+#define ID_AA64MMFR0_ASID_8            0x0
+#define ID_AA64MMFR0_ASID_16           0x2
+
 #define ID_AA64MMFR0_TGRAN4_NI                 0xf
 #define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN      0x0
 #define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX      0x7
@@ -857,9 +859,16 @@
 #define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN     0x1
 #define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX     0xf
 
+#define ID_AA64MMFR0_PARANGE_32                0x0
+#define ID_AA64MMFR0_PARANGE_36                0x1
+#define ID_AA64MMFR0_PARANGE_40                0x2
+#define ID_AA64MMFR0_PARANGE_42                0x3
+#define ID_AA64MMFR0_PARANGE_44                0x4
 #define ID_AA64MMFR0_PARANGE_48                0x5
 #define ID_AA64MMFR0_PARANGE_52                0x6
 
+#define ARM64_MIN_PARANGE_BITS         32
+
 #define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT 0x0
 #define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE    0x1
 #define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN     0x2
@@ -904,6 +913,7 @@
 #define ID_AA64MMFR2_CNP_SHIFT         0
 
 /* id_aa64dfr0 */
+#define ID_AA64DFR0_MTPMU_SHIFT                48
 #define ID_AA64DFR0_TRBE_SHIFT         44
 #define ID_AA64DFR0_TRACE_FILT_SHIFT   40
 #define ID_AA64DFR0_DOUBLELOCK_SHIFT   36
@@ -1034,14 +1044,17 @@
 #define ID_AA64MMFR0_TGRAN_SHIFT               ID_AA64MMFR0_TGRAN4_SHIFT
 #define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN       ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN
 #define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX       ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX
+#define ID_AA64MMFR0_TGRAN_2_SHIFT             ID_AA64MMFR0_TGRAN4_2_SHIFT
 #elif defined(CONFIG_ARM64_16K_PAGES)
 #define ID_AA64MMFR0_TGRAN_SHIFT               ID_AA64MMFR0_TGRAN16_SHIFT
 #define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN       ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN
 #define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX       ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX
+#define ID_AA64MMFR0_TGRAN_2_SHIFT             ID_AA64MMFR0_TGRAN16_2_SHIFT
 #elif defined(CONFIG_ARM64_64K_PAGES)
 #define ID_AA64MMFR0_TGRAN_SHIFT               ID_AA64MMFR0_TGRAN64_SHIFT
 #define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN       ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN
 #define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX       ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX
+#define ID_AA64MMFR0_TGRAN_2_SHIFT             ID_AA64MMFR0_TGRAN64_2_SHIFT
 #endif
 
 #define MVFR2_FPMISC_SHIFT             4
@@ -1172,6 +1185,11 @@
 #define ICH_VTR_A3V_SHIFT      21
 #define ICH_VTR_A3V_MASK       (1 << ICH_VTR_A3V_SHIFT)
 
+#define ARM64_FEATURE_FIELD_BITS       4
+
+/* Create a mask for the feature bits of the specified feature. */
+#define ARM64_FEATURE_MASK(x)  (GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT))
+
 #ifdef __ASSEMBLY__
 
        .irp    num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30