Merge tag 'soc-dt-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

[linux-2.6-microblaze.git] / arch / arm64 / boot / dts / ti / k3-j721e-main.dtsi

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 2569b4c..c7eafbc 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -1,8 +1,8 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
 /*
  * Device Tree Source for J721E SoC Family Main Domain peripherals
  *
- * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
  */
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/phy/phy-ti.h>
@@ -45,15 +45,15 @@
                ranges = <0x0 0x0 0x00100000 0x1c000>;
 
                serdes_ln_ctrl: mux-controller@4080 {
-                       compatible = "mmio-mux";
-                       reg = <0x00004080 0x50>;
+                       compatible = "reg-mux";
+                       reg = <0x4080 0x50>;
                        #mux-control-cells = <1>;
-                       mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
-                                       <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
-                                       <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
-                                       <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
-                                       <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
-                                       /* SERDES4 lane0/1/2/3 select */
+                       mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
+                                       <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
+                                       <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
+                                       <0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */
+                                       <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
+                                       <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */
                        idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
                                      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
                                      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
@@ -70,10 +70,11 @@
                };
 
                usb_serdes_mux: mux-controller@4000 {
-                       compatible = "mmio-mux";
+                       compatible = "reg-mux";
+                       reg = <0x4000 0x20>;
                        #mux-control-cells = <1>;
-                       mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
-                                       <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
+                       mux-reg-masks = <0x0 0x8000000>, /* USB0 to SERDES0/3 mux */
+                                       <0x10 0x8000000>; /* USB1 to SERDES1/2 mux */
                };
 
                ehrpwm_tbclk: clock-controller@4140 {
@@ -572,6 +573,128 @@
                pinctrl-single,function-mask = <0x0000001f>;
        };
 
+       ti_csi2rx0: ticsi2rx@4500000 {
+               compatible = "ti,j721e-csi2rx-shim";
+               reg = <0x0 0x4500000 0x0 0x1000>;
+               ranges;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               dmas = <&main_udmap 0x4940>;
+               dma-names = "rx0";
+               power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
+
+               cdns_csi2rx0: csi-bridge@4504000 {
+                       compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
+                       reg = <0x0 0x4504000 0x0 0x1000>;
+                       clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
+                               <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>;
+                       clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+                               "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+                       phys = <&dphy0>;
+                       phy-names = "dphy";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               csi0_port0: port@0 {
+                                       reg = <0>;
+                                       status = "disabled";
+                               };
+
+                               csi0_port1: port@1 {
+                                       reg = <1>;
+                                       status = "disabled";
+                               };
+
+                               csi0_port2: port@2 {
+                                       reg = <2>;
+                                       status = "disabled";
+                               };
+
+                               csi0_port3: port@3 {
+                                       reg = <3>;
+                                       status = "disabled";
+                               };
+
+                               csi0_port4: port@4 {
+                                       reg = <4>;
+                                       status = "disabled";
+                               };
+                       };
+               };
+       };
+
+       ti_csi2rx1: ticsi2rx@4510000 {
+               compatible = "ti,j721e-csi2rx-shim";
+               reg = <0x0 0x4510000 0x0 0x1000>;
+               ranges;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               dmas = <&main_udmap 0x4960>;
+               dma-names = "rx0";
+               power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
+
+               cdns_csi2rx1: csi-bridge@4514000 {
+                       compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
+                       reg = <0x0 0x4514000 0x0 0x1000>;
+                       clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>,
+                                <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>;
+                       clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+                                     "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+                       phys = <&dphy1>;
+                       phy-names = "dphy";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               csi1_port0: port@0 {
+                                       reg = <0>;
+                                       status = "disabled";
+                               };
+
+                               csi1_port1: port@1 {
+                                       reg = <1>;
+                                       status = "disabled";
+                               };
+
+                               csi1_port2: port@2 {
+                                       reg = <2>;
+                                       status = "disabled";
+                               };
+
+                               csi1_port3: port@3 {
+                                       reg = <3>;
+                                       status = "disabled";
+                               };
+
+                               csi1_port4: port@4 {
+                                       reg = <4>;
+                                       status = "disabled";
+                               };
+                       };
+               };
+       };
+
+       dphy0: phy@4580000 {
+               compatible = "cdns,dphy-rx";
+               reg = <0x0 0x4580000 0x0 0x1100>;
+               #phy-cells = <0>;
+               power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
+       };
+
+       dphy1: phy@4590000 {
+               compatible = "cdns,dphy-rx";
+               reg = <0x0 0x4590000 0x0 0x1100>;
+               #phy-cells = <0>;
+               power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
+       };
+
        serdes_wiz0: wiz@5000000 {
                compatible = "ti,j721e-wiz-16g";
                #address-cells = <1>;