Merge tag 'fscache-next-20210829' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-microblaze.git] / arch / arm64 / boot / dts / renesas / r8a77961.dtsi
index d980476..041473a 100644 (file)
 
                opp-500000000 {
                        opp-hz = /bits/ 64 <500000000>;
-                       opp-microvolt = <820000>;
+                       opp-microvolt = <830000>;
                        clock-latency-ns = <300000>;
                };
                opp-1000000000 {
                        opp-hz = /bits/ 64 <1000000000>;
-                       opp-microvolt = <820000>;
+                       opp-microvolt = <830000>;
                        clock-latency-ns = <300000>;
                };
                opp-1500000000 {
                        opp-hz = /bits/ 64 <1500000000>;
-                       opp-microvolt = <820000>;
+                       opp-microvolt = <830000>;
                        clock-latency-ns = <300000>;
+                       opp-suspend;
                };
                opp-1600000000 {
                        opp-hz = /bits/ 64 <1600000000>;
                };
 
                intc_ex: interrupt-controller@e61c0000 {
+                       compatible = "renesas,intc-ex-r8a77961", "renesas,irqc";
                        #interrupt-cells = <2>;
                        interrupt-controller;
                        reg = <0 0xe61c0000 0 0x200>;
-                       /* placeholder */
+                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 407>;
+                       power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
+                       resets = <&cpg 407>;
                };
 
                tmu0: timer@e61e0000 {
                        resets = <&cpg 219>;
                        #dma-cells = <1>;
                        dma-channels = <16>;
+                       iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
+                              <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
+                              <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
+                              <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
+                              <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
+                              <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
+                              <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
+                              <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
                };
 
                dmac1: dma-controller@e7300000 {
                        resets = <&cpg 218>;
                        #dma-cells = <1>;
                        dma-channels = <16>;
+                       iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
+                              <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
+                              <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
+                              <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
+                              <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
+                              <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
+                              <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
+                              <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
                };
 
                dmac2: dma-controller@e7310000 {
                        resets = <&cpg 217>;
                        #dma-cells = <1>;
                        dma-channels = <16>;
+                       iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
+                              <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
+                              <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
+                              <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
+                              <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
+                              <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
+                              <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
+                              <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
                };
 
                ipmmu_ds0: iommu@e6740000 {
                                          "ch20", "ch21", "ch22", "ch23",
                                          "ch24";
                        clocks = <&cpg CPG_MOD 812>;
+                       clock-names = "fck";
                        power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
                        resets = <&cpg 812>;
                        phy-mode = "rgmii";
                        rx-internal-delay-ps = <0>;
                        tx-internal-delay-ps = <0>;
+                       iommus = <&ipmmu_ds0 16>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        status = "disabled";
                        max-frequency = <200000000>;
                        power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
                        resets = <&cpg 314>;
+                       iommus = <&ipmmu_ds1 32>;
                        status = "disabled";
                };
 
                        max-frequency = <200000000>;
                        power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
                        resets = <&cpg 313>;
+                       iommus = <&ipmmu_ds1 33>;
                        status = "disabled";
                };
 
                        max-frequency = <200000000>;
                        power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
                        resets = <&cpg 312>;
+                       iommus = <&ipmmu_ds1 34>;
                        status = "disabled";
                };
 
                        max-frequency = <200000000>;
                        power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
                        resets = <&cpg 311>;
+                       iommus = <&ipmmu_ds1 35>;
                        status = "disabled";
                };