Merge tag 'for-5.15/io_uring-2021-09-04' of git://git.kernel.dk/linux-block
[linux-2.6-microblaze.git] / arch / arm64 / boot / dts / qcom / sdm630.dtsi
index 082fa5c..9153e66 100644 (file)
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2020, Konrad Dybcio
+ * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
+ * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
  */
 
 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
@@ -10,6 +11,7 @@
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,apr.h>
 
 / {
        interrupt-parent = <&intc>;
        chosen { };
 
        clocks {
-               xo_board: xo_board {
+               xo_board: xo-board {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
                        clock-frequency = <19200000>;
                        clock-output-names = "xo_board";
                };
 
-               sleep_clk: sleep_clk {
+               sleep_clk: sleep-clk {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
                        clock-frequency = <32764>;
                };
        };
 
-       memory {
+       memory@80000000 {
                device_type = "memory";
                /* We expect the bootloader to fill in the reg */
-               reg = <0 0 0 0>;
+               reg = <0x0 0x80000000 0x0 0x0>;
        };
 
        pmu {
                hwlocks = <&tcsr_mutex 3>;
        };
 
+       smp2p-adsp {
+               compatible = "qcom,smp2p";
+               qcom,smem = <443>, <429>;
+               interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
+               mboxes = <&apcs_glb 10>;
+               qcom,local-pid = <0>;
+               qcom,remote-pid = <2>;
+
+               adsp_smp2p_out: master-kernel {
+                       qcom,entry-name = "master-kernel";
+                       #qcom,smem-state-cells = <1>;
+               };
+
+               adsp_smp2p_in: slave-kernel {
+                       qcom,entry-name = "slave-kernel";
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+       };
+
+       smp2p-mpss {
+               compatible = "qcom,smp2p";
+               qcom,smem = <435>, <428>;
+               interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
+               mboxes = <&apcs_glb 14>;
+               qcom,local-pid = <0>;
+               qcom,remote-pid = <1>;
+
+               modem_smp2p_out: master-kernel {
+                       qcom,entry-name = "master-kernel";
+                       #qcom,smem-state-cells = <1>;
+               };
+
+               modem_smp2p_in: slave-kernel {
+                       qcom,entry-name = "slave-kernel";
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+       };
+
        soc {
                #address-cells = <1>;
                #size-cells = <1>;
 
                tcsr_mutex_regs: syscon@1f40000 {
                        compatible = "syscon";
-                       reg = <0x01f40000 0x20000>;
+                       reg = <0x01f40000 0x40000>;
                };
 
                tlmm: pinctrl@3100000 {
 
                        i2c1_default: i2c1-default {
                                pins = "gpio2", "gpio3";
+                               function = "blsp_i2c1";
                                drive-strength = <2>;
                                bias-disable;
                        };
 
                        i2c1_sleep: i2c1-sleep {
                                pins = "gpio2", "gpio3";
+                               function = "blsp_i2c1";
                                drive-strength = <2>;
                                bias-pull-up;
                        };
 
                        i2c2_default: i2c2-default {
                                pins = "gpio6", "gpio7";
+                               function = "blsp_i2c2";
                                drive-strength = <2>;
                                bias-disable;
                        };
 
                        i2c2_sleep: i2c2-sleep {
                                pins = "gpio6", "gpio7";
+                               function = "blsp_i2c2";
                                drive-strength = <2>;
                                bias-pull-up;
                        };
 
                        i2c3_default: i2c3-default {
                                pins = "gpio10", "gpio11";
+                               function = "blsp_i2c3";
                                drive-strength = <2>;
                                bias-disable;
                        };
 
                        i2c3_sleep: i2c3-sleep {
                                pins = "gpio10", "gpio11";
+                               function = "blsp_i2c3";
                                drive-strength = <2>;
                                bias-pull-up;
                        };
 
                        i2c4_default: i2c4-default {
                                pins = "gpio14", "gpio15";
+                               function = "blsp_i2c4";
                                drive-strength = <2>;
                                bias-disable;
                        };
 
                        i2c4_sleep: i2c4-sleep {
                                pins = "gpio14", "gpio15";
+                               function = "blsp_i2c4";
                                drive-strength = <2>;
                                bias-pull-up;
                        };
 
                        i2c5_default: i2c5-default {
                                pins = "gpio18", "gpio19";
+                               function = "blsp_i2c5";
                                drive-strength = <2>;
                                bias-disable;
                        };
 
                        i2c5_sleep: i2c5-sleep {
                                pins = "gpio18", "gpio19";
+                               function = "blsp_i2c5";
                                drive-strength = <2>;
                                bias-pull-up;
                        };
 
                        i2c6_default: i2c6-default {
                                pins = "gpio22", "gpio23";
+                               function = "blsp_i2c6";
                                drive-strength = <2>;
                                bias-disable;
                        };
 
                        i2c6_sleep: i2c6-sleep {
                                pins = "gpio22", "gpio23";
+                               function = "blsp_i2c6";
                                drive-strength = <2>;
                                bias-pull-up;
                        };
 
                        i2c7_default: i2c7-default {
                                pins = "gpio26", "gpio27";
+                               function = "blsp_i2c7";
                                drive-strength = <2>;
                                bias-disable;
                        };
 
                        i2c7_sleep: i2c7-sleep {
                                pins = "gpio26", "gpio27";
+                               function = "blsp_i2c7";
                                drive-strength = <2>;
                                bias-pull-up;
                        };
 
                        i2c8_default: i2c8-default {
                                pins = "gpio30", "gpio31";
+                               function = "blsp_i2c8";
                                drive-strength = <2>;
                                bias-disable;
                        };
 
                        i2c8_sleep: i2c8-sleep {
                                pins = "gpio30", "gpio31";
+                               function = "blsp_i2c8";
                                drive-strength = <2>;
                                bias-pull-up;
                        };
 
+                       cci0_default: cci0_default {
+                               pinmux {
+                                       pins = "gpio36","gpio37";
+                                       function = "cci_i2c";
+                               };
+
+                               pinconf {
+                                       pins = "gpio36","gpio37";
+                                       bias-pull-up;
+                                       drive-strength = <2>;
+                               };
+                       };
+
+                       cci1_default: cci1_default {
+                               pinmux {
+                                       pins = "gpio38","gpio39";
+                                       function = "cci_i2c";
+                               };
+
+                               pinconf {
+                                       pins = "gpio38","gpio39";
+                                       bias-pull-up;
+                                       drive-strength = <2>;
+                               };
+                       };
+
                        sdc1_state_on: sdc1-on {
                                clk {
                                        pins = "sdc1_clk";
                        };
                };
 
+               adreno_gpu: gpu@5000000 {
+                       compatible = "qcom,adreno-508.0", "qcom,adreno";
+                       #stream-id-cells = <16>;
+
+                       reg = <0x05000000 0x40000>;
+                       reg-names = "kgsl_3d0_reg_memory";
+
+                       interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+
+                       clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
+                               <&gpucc GPUCC_RBBMTIMER_CLK>,
+                               <&gcc GCC_BIMC_GFX_CLK>,
+                               <&gcc GCC_GPU_BIMC_GFX_CLK>,
+                               <&gpucc GPUCC_RBCPR_CLK>,
+                               <&gpucc GPUCC_GFX3D_CLK>;
+
+                       clock-names = "iface",
+                               "rbbmtimer",
+                               "mem",
+                               "mem_iface",
+                               "rbcpr",
+                               "core";
+
+                       power-domains = <&rpmpd SDM660_VDDMX>;
+                       iommus = <&kgsl_smmu 0>;
+
+                       nvmem-cells = <&gpu_speed_bin>;
+                       nvmem-cell-names = "speed_bin";
+
+                       interconnects = <&gnoc 1 &bimc 5>;
+                       interconnect-names = "gfx-mem";
+
+                       operating-points-v2 = <&gpu_sdm630_opp_table>;
+
+                       gpu_sdm630_opp_table: opp-table {
+                               compatible  = "operating-points-v2";
+                               opp-775000000 {
+                                       opp-hz = /bits/ 64 <775000000>;
+                                       opp-level = <RPM_SMD_LEVEL_TURBO>;
+                                       opp-peak-kBps = <5412000>;
+                                       opp-supported-hw = <0xA2>;
+                               };
+                               opp-647000000 {
+                                       opp-hz = /bits/ 64 <647000000>;
+                                       opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
+                                       opp-peak-kBps = <4068000>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+                               opp-588000000 {
+                                       opp-hz = /bits/ 64 <588000000>;
+                                       opp-level = <RPM_SMD_LEVEL_NOM>;
+                                       opp-peak-kBps = <3072000>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+                               opp-465000000 {
+                                       opp-hz = /bits/ 64 <465000000>;
+                                       opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
+                                       opp-peak-kBps = <2724000>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+                               opp-370000000 {
+                                       opp-hz = /bits/ 64 <370000000>;
+                                       opp-level = <RPM_SMD_LEVEL_SVS>;
+                                       opp-peak-kBps = <2188000>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+                               opp-240000000 {
+                                       opp-hz = /bits/ 64 <240000000>;
+                                       opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
+                                       opp-peak-kBps = <1648000>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+                               opp-160000000 {
+                                       opp-hz = /bits/ 64 <160000000>;
+                                       opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
+                                       opp-peak-kBps = <1200000>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+                       };
+               };
+
                kgsl_smmu: iommu@5040000 {
                        compatible = "qcom,sdm630-smmu-v2",
                                     "qcom,adreno-smmu", "qcom,smmu-v2";
                                        <&gcc GCC_BLSP1_AHB_CLK>;
                        clock-names = "core", "iface";
                        clock-frequency = <400000>;
+                       dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
+                       dma-names = "tx", "rx";
 
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&i2c1_default>;
                                 <&gcc GCC_BLSP1_AHB_CLK>;
                        clock-names = "core", "iface";
                        clock-frequency = <400000>;
+                       dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
+                       dma-names = "tx", "rx";
 
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&i2c2_default>;
                                 <&gcc GCC_BLSP1_AHB_CLK>;
                        clock-names = "core", "iface";
                        clock-frequency = <400000>;
+                       dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
+                       dma-names = "tx", "rx";
 
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&i2c3_default>;
                                 <&gcc GCC_BLSP1_AHB_CLK>;
                        clock-names = "core", "iface";
                        clock-frequency = <400000>;
+                       dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
+                       dma-names = "tx", "rx";
 
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&i2c4_default>;
                                 <&gcc GCC_BLSP2_AHB_CLK>;
                        clock-names = "core", "iface";
                        clock-frequency = <400000>;
+                       dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
+                       dma-names = "tx", "rx";
 
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&i2c5_default>;
                                 <&gcc GCC_BLSP2_AHB_CLK>;
                        clock-names = "core", "iface";
                        clock-frequency = <400000>;
+                       dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
+                       dma-names = "tx", "rx";
 
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&i2c6_default>;
                                 <&gcc GCC_BLSP2_AHB_CLK>;
                        clock-names = "core", "iface";
                        clock-frequency = <400000>;
+                       dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
+                       dma-names = "tx", "rx";
 
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&i2c7_default>;
                                 <&gcc GCC_BLSP2_AHB_CLK>;
                        clock-names = "core", "iface";
                        clock-frequency = <400000>;
+                       dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
+                       dma-names = "tx", "rx";
 
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&i2c8_default>;
                        status = "disabled";
                };
 
+               imem@146bf000 {
+                       compatible = "simple-mfd";
+                       reg = <0x146bf000 0x1000>;
+
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       ranges = <0 0x146bf000 0x1000>;
+
+                       pil-reloc@94c {
+                               compatible = "qcom,pil-reloc-info";
+                               reg = <0x94c 0xc8>;
+                       };
+               };
+
+               camss: camss@ca00000 {
+                       compatible = "qcom,sdm660-camss";
+                       reg = <0x0c824000 0x1000>,
+                             <0x0ca00120 0x4>,
+                             <0x0c825000 0x1000>,
+                             <0x0ca00124 0x4>,
+                             <0x0c826000 0x1000>,
+                             <0x0ca00128 0x4>,
+                             <0x0ca30000 0x100>,
+                             <0x0ca30400 0x100>,
+                             <0x0ca30800 0x100>,
+                             <0x0ca30c00 0x100>,
+                             <0x0ca31000 0x500>,
+                             <0x0ca00020 0x10>,
+                             <0x0ca10000 0x1000>,
+                             <0x0ca14000 0x1000>;
+                       reg-names = "csiphy0",
+                                   "csiphy0_clk_mux",
+                                   "csiphy1",
+                                   "csiphy1_clk_mux",
+                                   "csiphy2",
+                                   "csiphy2_clk_mux",
+                                   "csid0",
+                                   "csid1",
+                                   "csid2",
+                                   "csid3",
+                                   "ispif",
+                                   "csi_clk_mux",
+                                   "vfe0",
+                                   "vfe1";
+                       interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "csiphy0",
+                                         "csiphy1",
+                                         "csiphy2",
+                                         "csid0",
+                                         "csid1",
+                                         "csid2",
+                                         "csid3",
+                                         "ispif",
+                                         "vfe0",
+                                         "vfe1";
+                       clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
+                               <&mmcc THROTTLE_CAMSS_AXI_CLK>,
+                               <&mmcc CAMSS_ISPIF_AHB_CLK>,
+                               <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
+                               <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
+                               <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
+                               <&mmcc CAMSS_CSI0_AHB_CLK>,
+                               <&mmcc CAMSS_CSI0_CLK>,
+                               <&mmcc CAMSS_CPHY_CSID0_CLK>,
+                               <&mmcc CAMSS_CSI0PIX_CLK>,
+                               <&mmcc CAMSS_CSI0RDI_CLK>,
+                               <&mmcc CAMSS_CSI1_AHB_CLK>,
+                               <&mmcc CAMSS_CSI1_CLK>,
+                               <&mmcc CAMSS_CPHY_CSID1_CLK>,
+                               <&mmcc CAMSS_CSI1PIX_CLK>,
+                               <&mmcc CAMSS_CSI1RDI_CLK>,
+                               <&mmcc CAMSS_CSI2_AHB_CLK>,
+                               <&mmcc CAMSS_CSI2_CLK>,
+                               <&mmcc CAMSS_CPHY_CSID2_CLK>,
+                               <&mmcc CAMSS_CSI2PIX_CLK>,
+                               <&mmcc CAMSS_CSI2RDI_CLK>,
+                               <&mmcc CAMSS_CSI3_AHB_CLK>,
+                               <&mmcc CAMSS_CSI3_CLK>,
+                               <&mmcc CAMSS_CPHY_CSID3_CLK>,
+                               <&mmcc CAMSS_CSI3PIX_CLK>,
+                               <&mmcc CAMSS_CSI3RDI_CLK>,
+                               <&mmcc CAMSS_AHB_CLK>,
+                               <&mmcc CAMSS_VFE0_CLK>,
+                               <&mmcc CAMSS_CSI_VFE0_CLK>,
+                               <&mmcc CAMSS_VFE0_AHB_CLK>,
+                               <&mmcc CAMSS_VFE0_STREAM_CLK>,
+                               <&mmcc CAMSS_VFE1_CLK>,
+                               <&mmcc CAMSS_CSI_VFE1_CLK>,
+                               <&mmcc CAMSS_VFE1_AHB_CLK>,
+                               <&mmcc CAMSS_VFE1_STREAM_CLK>,
+                               <&mmcc CAMSS_VFE_VBIF_AHB_CLK>,
+                               <&mmcc CAMSS_VFE_VBIF_AXI_CLK>,
+                               <&mmcc CSIPHY_AHB2CRIF_CLK>,
+                               <&mmcc CAMSS_CPHY_CSID0_CLK>,
+                               <&mmcc CAMSS_CPHY_CSID1_CLK>,
+                               <&mmcc CAMSS_CPHY_CSID2_CLK>,
+                               <&mmcc CAMSS_CPHY_CSID3_CLK>;
+                       clock-names = "top_ahb",
+                               "throttle_axi",
+                               "ispif_ahb",
+                               "csiphy0_timer",
+                               "csiphy1_timer",
+                               "csiphy2_timer",
+                               "csi0_ahb",
+                               "csi0",
+                               "csi0_phy",
+                               "csi0_pix",
+                               "csi0_rdi",
+                               "csi1_ahb",
+                               "csi1",
+                               "csi1_phy",
+                               "csi1_pix",
+                               "csi1_rdi",
+                               "csi2_ahb",
+                               "csi2",
+                               "csi2_phy",
+                               "csi2_pix",
+                               "csi2_rdi",
+                               "csi3_ahb",
+                               "csi3",
+                               "csi3_phy",
+                               "csi3_pix",
+                               "csi3_rdi",
+                               "ahb",
+                               "vfe0",
+                               "csi_vfe0",
+                               "vfe0_ahb",
+                               "vfe0_stream",
+                               "vfe1",
+                               "csi_vfe1",
+                               "vfe1_ahb",
+                               "vfe1_stream",
+                               "vfe_ahb",
+                               "vfe_axi",
+                               "csiphy_ahb2crif",
+                               "cphy_csid0",
+                               "cphy_csid1",
+                               "cphy_csid2",
+                               "cphy_csid3";
+                       interconnects = <&mnoc 5 &bimc 5>;
+                       interconnect-names = "vfe-mem";
+                       iommus = <&mmss_smmu 0xc00>,
+                                <&mmss_smmu 0xc01>,
+                                <&mmss_smmu 0xc02>,
+                                <&mmss_smmu 0xc03>;
+                       power-domains = <&mmcc CAMSS_VFE0_GDSC>,
+                                       <&mmcc CAMSS_VFE1_GDSC>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+               };
+
+               cci: cci@ca0c000 {
+                       compatible = "qcom,msm8996-cci";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0ca0c000 0x1000>;
+                       interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
+
+                       assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
+                                         <&mmcc CAMSS_CCI_CLK>;
+                       assigned-clock-rates = <80800000>, <37500000>;
+                       clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
+                                <&mmcc CAMSS_CCI_AHB_CLK>,
+                                <&mmcc CAMSS_CCI_CLK>,
+                                <&mmcc CAMSS_AHB_CLK>;
+                       clock-names = "camss_top_ahb",
+                                     "cci_ahb",
+                                     "cci",
+                                     "camss_ahb";
+
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&cci0_default &cci1_default>;
+                       power-domains = <&mmcc CAMSS_TOP_GDSC>;
+                       status = "disabled";
+
+                       cci_i2c0: i2c-bus@0 {
+                               reg = <0>;
+                               clock-frequency = <400000>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+
+                       cci_i2c1: i2c-bus@1 {
+                               reg = <1>;
+                               clock-frequency = <400000>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+               };
+
                mmss_smmu: iommu@cd00000 {
                        compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
                        reg = <0x0cd00000 0x40000>;
                        status = "disabled";
                };
 
+               adsp_pil: remoteproc@15700000 {
+                       compatible = "qcom,sdm660-adsp-pas";
+                       reg = <0x15700000 0x4040>;
+
+                       interrupts-extended =
+                               <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "wdog", "fatal", "ready",
+                                         "handover", "stop-ack";
+
+                       clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+                       clock-names = "xo";
+
+                       memory-region = <&adsp_region>;
+                       power-domains = <&rpmpd SDM660_VDDCX>;
+                       power-domain-names = "cx";
+
+                       qcom,smem-states = <&adsp_smp2p_out 0>;
+                       qcom,smem-state-names = "stop";
+
+                       glink-edge {
+                               interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
+
+                               label = "lpass";
+                               mboxes = <&apcs_glb 9>;
+                               qcom,remote-pid = <2>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               apr {
+                                       compatible = "qcom,apr-v2";
+                                       qcom,glink-channels = "apr_audio_svc";
+                                       qcom,apr-domain = <APR_DOMAIN_ADSP>;
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       q6core {
+                                               reg = <APR_SVC_ADSP_CORE>;
+                                               compatible = "qcom,q6core";
+                                       };
+
+                                       q6afe: apr-service@4 {
+                                               compatible = "qcom,q6afe";
+                                               reg = <APR_SVC_AFE>;
+                                               q6afedai: dais {
+                                                       compatible = "qcom,q6afe-dais";
+                                                       #address-cells = <1>;
+                                                       #size-cells = <0>;
+                                                       #sound-dai-cells = <1>;
+                                               };
+                                       };
+
+                                       q6asm: apr-service@7 {
+                                               compatible = "qcom,q6asm";
+                                               reg = <APR_SVC_ASM>;
+                                               q6asmdai: dais {
+                                                       compatible = "qcom,q6asm-dais";
+                                                       #address-cells = <1>;
+                                                       #size-cells = <0>;
+                                                       #sound-dai-cells = <1>;
+                                                       iommus = <&lpass_smmu 1>;
+                                               };
+                                       };
+
+                                       q6adm: apr-service@8 {
+                                               compatible = "qcom,q6adm";
+                                               reg = <APR_SVC_ADM>;
+                                               q6routing: routing {
+                                                       compatible = "qcom,q6adm-routing";
+                                                       #sound-dai-cells = <0>;
+                                               };
+                                       };
+                               };
+                       };
+               };
+
                gnoc: interconnect@17900000 {
                        compatible = "qcom,sdm660-gnoc";
                        reg = <0x17900000 0xe000>;
                #hwlock-cells = <1>;
        };
 
+       sound: sound {
+       };
+
+       thermal-zones {
+               aoss-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens 0>;
+
+                       trips {
+                               aoss_alert0: trip-point0 {
+                                       temperature = <105000>;
+                                       hysteresis = <1000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               cpuss0-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens 1>;
+
+                       trips {
+                               cpuss0_alert0: trip-point0 {
+                                       temperature = <125000>;
+                                       hysteresis = <1000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               cpuss1-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens 2>;
+
+                       trips {
+                               cpuss1_alert0: trip-point0 {
+                                       temperature = <125000>;
+                                       hysteresis = <1000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+
+               cpu0-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens 3>;
+
+                       trips {
+                               cpu0_alert0: trip-point0 {
+                                       temperature = <70000>;
+                                       hysteresis = <1000>;
+                                       type = "passive";
+                               };
+
+                               cpu0_crit: cpu_crit {
+                                       temperature = <110000>;
+                                       hysteresis = <1000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               cpu1-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens 4>;
+
+                       trips {
+                               cpu1_alert0: trip-point0 {
+                                       temperature = <70000>;
+                                       hysteresis = <1000>;
+                                       type = "passive";
+                               };
+
+                               cpu1_crit: cpu_crit {
+                                       temperature = <110000>;
+                                       hysteresis = <1000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               cpu2-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens 5>;
+
+                       trips {
+                               cpu2_alert0: trip-point0 {
+                                       temperature = <70000>;
+                                       hysteresis = <1000>;
+                                       type = "passive";
+                               };
+
+                               cpu2_crit: cpu_crit {
+                                       temperature = <110000>;
+                                       hysteresis = <1000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               cpu3-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens 6>;
+
+                       trips {
+                               cpu3_alert0: trip-point0 {
+                                       temperature = <70000>;
+                                       hysteresis = <1000>;
+                                       type = "passive";
+                               };
+
+                               cpu3_crit: cpu_crit {
+                                       temperature = <110000>;
+                                       hysteresis = <1000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               /*
+                * According to what downstream DTS says,
+                * the entire power efficient cluster has
+                * only a single thermal sensor.
+                */
+
+               pwr-cluster-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens 7>;
+
+                       trips {
+                               pwr_cluster_alert0: trip-point0 {
+                                       temperature = <70000>;
+                                       hysteresis = <1000>;
+                                       type = "passive";
+                               };
+
+                               pwr_cluster_crit: cpu_crit {
+                                       temperature = <110000>;
+                                       hysteresis = <1000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               gpu-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+
+                       thermal-sensors = <&tsens 8>;
+
+                       trips {
+                               gpu_alert0: trip-point0 {
+                                       temperature = <90000>;
+                                       hysteresis = <1000>;
+                                       type = "hot";
+                               };
+                       };
+               };
+       };
+
        timer {
                compatible = "arm,armv8-timer";
                interrupts = <GIC_PPI 1 0xf08>,