arm64: dts: qcom: ipq8074: switch PCIe QMP PHY to new style of bindings

[linux-2.6-microblaze.git] / arch / arm64 / boot / dts / qcom / ipq8074.dtsi

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 00ed719..3350804 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -211,59 +211,48 @@
 
                pcie_qmp0: phy@84000 {
                        compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
-                       reg = <0x00084000 0x1bc>;
-                       #address-cells = <1>;
-                       #size-cells = <1>;
-                       ranges;
+                       reg = <0x00084000 0x1000>;
 
                        clocks = <&gcc GCC_PCIE0_AUX_CLK>,
-                               <&gcc GCC_PCIE0_AHB_CLK>;
-                       clock-names = "aux", "cfg_ahb";
+                                <&gcc GCC_PCIE0_AHB_CLK>,
+                                <&gcc GCC_PCIE0_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "cfg_ahb",
+                                     "pipe";
+
+                       clock-output-names = "pcie20_phy0_pipe_clk";
+                       #clock-cells = <0>;
+
+                       #phy-cells = <0>;
+
                        resets = <&gcc GCC_PCIE0_PHY_BCR>,
-                               <&gcc GCC_PCIE0PHY_PHY_BCR>;
+                                <&gcc GCC_PCIE0PHY_PHY_BCR>;
                        reset-names = "phy",
                                      "common";
                        status = "disabled";
-
-                       pcie_phy0: phy@84200 {
-                               reg = <0x84200 0x16c>,
-                                     <0x84400 0x200>,
-                                     <0x84800 0x1f0>,
-                                     <0x84c00 0xf4>;
-                               #phy-cells = <0>;
-                               #clock-cells = <0>;
-                               clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
-                               clock-names = "pipe0";
-                               clock-output-names = "pcie20_phy0_pipe_clk";
-                       };
                };
 
                pcie_qmp1: phy@8e000 {
                        compatible = "qcom,ipq8074-qmp-pcie-phy";
-                       reg = <0x0008e000 0x1c4>;
-                       #address-cells = <1>;
-                       #size-cells = <1>;
-                       ranges;
+                       reg = <0x0008e000 0x1000>;
 
                        clocks = <&gcc GCC_PCIE1_AUX_CLK>,
-                               <&gcc GCC_PCIE1_AHB_CLK>;
-                       clock-names = "aux", "cfg_ahb";
+                                <&gcc GCC_PCIE1_AHB_CLK>,
+                                <&gcc GCC_PCIE1_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "cfg_ahb",
+                                     "pipe";
+
+                       clock-output-names = "pcie20_phy1_pipe_clk";
+                       #clock-cells = <0>;
+
+                       #phy-cells = <0>;
+
                        resets = <&gcc GCC_PCIE1_PHY_BCR>,
-                               <&gcc GCC_PCIE1PHY_PHY_BCR>;
+                                <&gcc GCC_PCIE1PHY_PHY_BCR>;
                        reset-names = "phy",
                                      "common";
                        status = "disabled";
-
-                       pcie_phy1: phy@8e200 {
-                               reg = <0x8e200 0x130>,
-                                     <0x8e400 0x200>,
-                                     <0x8e800 0x1f8>;
-                               #phy-cells = <0>;
-                               #clock-cells = <0>;
-                               clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
-                               clock-names = "pipe0";
-                               clock-output-names = "pcie20_phy1_pipe_clk";
-                       };
                };
 
                mdio: mdio@90000 {
@@ -807,7 +796,7 @@
                        #address-cells = <3>;
                        #size-cells = <2>;
 
-                       phys = <&pcie_phy1>;
+                       phys = <&pcie_qmp1>;
                        phy-names = "pciephy";
 
                        ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>,   /* I/O */
@@ -869,7 +858,7 @@
                        #address-cells = <3>;
                        #size-cells = <2>;
 
-                       phys = <&pcie_phy0>;
+                       phys = <&pcie_qmp0>;
                        phy-names = "pciephy";
 
                        ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>,   /* I/O */