Merge tag 'block-5.14-2021-08-07' of git://git.kernel.dk/linux-block

[linux-2.6-microblaze.git] / arch / arm64 / boot / dts / mediatek / mt8173.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 003a565..22f271b 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -1459,14 +1459,11 @@
                        clock-names = "apb", "smi";
                };
 
-               vcodec_enc: vcodec@18002000 {
+               vcodec_enc_avc: vcodec@18002000 {
                        compatible = "mediatek,mt8173-vcodec-enc";
-                       reg = <0 0x18002000 0 0x1000>,  /* VENC_SYS */
-                             <0 0x19002000 0 0x1000>;  /* VENC_LT_SYS */
-                       interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
-                                    <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
-                       mediatek,larb = <&larb3>,
-                                       <&larb5>;
+                       reg = <0 0x18002000 0 0x1000>;  /* VENC_SYS */
+                       interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
+                       mediatek,larb = <&larb3>;
                        iommus = <&iommu M4U_PORT_VENC_RCPU>,
                                 <&iommu M4U_PORT_VENC_REC>,
                                 <&iommu M4U_PORT_VENC_BSDMA>,
@@ -1477,29 +1474,12 @@
                                 <&iommu M4U_PORT_VENC_REF_LUMA>,
                                 <&iommu M4U_PORT_VENC_REF_CHROMA>,
                                 <&iommu M4U_PORT_VENC_NBM_RDMA>,
-                                <&iommu M4U_PORT_VENC_NBM_WDMA>,
-                                <&iommu M4U_PORT_VENC_RCPU_SET2>,
-                                <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
-                                <&iommu M4U_PORT_VENC_BSDMA_SET2>,
-                                <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
-                                <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
-                                <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
-                                <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
-                                <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
-                                <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
+                                <&iommu M4U_PORT_VENC_NBM_WDMA>;
                        mediatek,vpu = <&vpu>;
-                       clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
-                                <&topckgen CLK_TOP_VENC_SEL>,
-                                <&topckgen CLK_TOP_UNIVPLL1_D2>,
-                                <&topckgen CLK_TOP_VENC_LT_SEL>;
-                       clock-names = "venc_sel_src",
-                                     "venc_sel",
-                                     "venc_lt_sel_src",
-                                     "venc_lt_sel";
-                       assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
-                                         <&topckgen CLK_TOP_VENC_LT_SEL>;
-                       assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>,
-                                                <&topckgen CLK_TOP_VCODECPLL_370P5>;
+                       clocks = <&topckgen CLK_TOP_VENC_SEL>;
+                       clock-names = "venc_sel";
+                       assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
+                       assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
                };
 
                jpegdec: jpegdec@18004000 {
@@ -1531,5 +1511,27 @@
                                 <&vencltsys CLK_VENCLT_CKE0>;
                        clock-names = "apb", "smi";
                };
+
+               vcodec_enc_vp8: vcodec@19002000 {
+                       compatible = "mediatek,mt8173-vcodec-enc-vp8";
+                       reg =  <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
+                       interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
+                       iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
+                                <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
+                                <&iommu M4U_PORT_VENC_BSDMA_SET2>,
+                                <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
+                                <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
+                                <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
+                                <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
+                                <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
+                                <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
+                       mediatek,larb = <&larb5>;
+                       mediatek,vpu = <&vpu>;
+                       clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
+                       clock-names = "venc_lt_sel";
+                       assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
+                       assigned-clock-parents =
+                                <&topckgen CLK_TOP_VCODECPLL_370P5>;
+               };
        };
 };