Merge branch 'work.iov_iter' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs

[linux-2.6-microblaze.git] / arch / arm64 / boot / dts / freescale / imx8mq.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 91df9c5..4066b16 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -193,7 +193,6 @@
                compatible = "arm,cortex-a53-pmu";
                interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-parent = <&gic>;
-               interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
        };
 
        psci {
@@ -1099,6 +1098,110 @@
                                status = "disabled";
                        };
 
+                       mipi_csi1: csi@30a70000 {
+                               compatible = "fsl,imx8mq-mipi-csi2";
+                               reg = <0x30a70000 0x1000>;
+                               clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
+                                  <&clk IMX8MQ_CLK_CSI1_ESC>,
+                                  <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
+                               clock-names = "core", "esc", "ui";
+                               assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
+                                   <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
+                                   <&clk IMX8MQ_CLK_CSI1_ESC>;
+                               assigned-clock-rates = <266000000>, <333000000>, <66000000>;
+                               assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
+                                       <&clk IMX8MQ_SYS2_PLL_1000M>,
+                                       <&clk IMX8MQ_SYS1_PLL_800M>;
+                               power-domains = <&pgc_mipi_csi1>;
+                               resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>,
+                                        <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>,
+                                        <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>;
+                               fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
+                               interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;
+                               interconnect-names = "dram";
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+
+                                               csi1_mipi_ep: endpoint {
+                                                       remote-endpoint = <&csi1_ep>;
+                                               };
+                                       };
+                               };
+                       };
+
+                       csi1: csi@30a90000 {
+                               compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
+                               reg = <0x30a90000 0x10000>;
+                               interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>;
+                               clock-names = "mclk";
+                               status = "disabled";
+
+                               port {
+                                       csi1_ep: endpoint {
+                                               remote-endpoint = <&csi1_mipi_ep>;
+                                       };
+                               };
+                       };
+
+                       mipi_csi2: csi@30b60000 {
+                               compatible = "fsl,imx8mq-mipi-csi2";
+                               reg = <0x30b60000 0x1000>;
+                               clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
+                                  <&clk IMX8MQ_CLK_CSI2_ESC>,
+                                  <&clk IMX8MQ_CLK_CSI2_PHY_REF>;
+                               clock-names = "core", "esc", "ui";
+                               assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
+                                   <&clk IMX8MQ_CLK_CSI2_PHY_REF>,
+                                   <&clk IMX8MQ_CLK_CSI2_ESC>;
+                               assigned-clock-rates = <266000000>, <333000000>, <66000000>;
+                               assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
+                                       <&clk IMX8MQ_SYS2_PLL_1000M>,
+                                       <&clk IMX8MQ_SYS1_PLL_800M>;
+                               power-domains = <&pgc_mipi_csi2>;
+                               resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>,
+                                        <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>,
+                                        <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>;
+                               fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
+                               interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>;
+                               interconnect-names = "dram";
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+
+                                               csi2_mipi_ep: endpoint {
+                                                       remote-endpoint = <&csi2_ep>;
+                                               };
+                                       };
+                               };
+                       };
+
+                       csi2: csi@30b80000 {
+                               compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
+                               reg = <0x30b80000 0x10000>;
+                               interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>;
+                               clock-names = "mclk";
+                               status = "disabled";
+
+                               port {
+                                       csi2_ep: endpoint {
+                                               remote-endpoint = <&csi2_mipi_ep>;
+                                       };
+                               };
+                       };
+
                        mu: mailbox@30aa0000 {
                                compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
                                reg = <0x30aa0000 0x10000>;