Merge branches 'pm-cpufreq', 'pm-sleep' and 'pm-em'
[linux-2.6-microblaze.git] / arch / arm64 / boot / dts / freescale / imx8mp.dtsi
index f4eaab3..9b07b26 100644 (file)
                clock-output-names = "clk_ext4";
        };
 
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               dsp_reserved: dsp@92400000 {
+                       reg = <0 0x92400000 0 0x2000000>;
+                       no-map;
+               };
+       };
+
        pmu {
                compatible = "arm,cortex-a53-pmu";
                interrupts = <GIC_PPI 7
                             (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-               interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
        };
 
        psci {
                                #mbox-cells = <2>;
                        };
 
+                       mu2: mailbox@30e60000 {
+                               compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
+                               reg = <0x30e60000 0x10000>;
+                               interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+                               #mbox-cells = <2>;
+                               status = "disabled";
+                       };
+
                        i2c5: i2c@30ad0000 {
                                compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
                                #address-cells = <1>;
                                snps,dis-u2-freeclk-exists-quirk;
                        };
                };
+
+               dsp: dsp@3b6e8000 {
+                       compatible = "fsl,imx8mp-dsp";
+                       reg = <0x3b6e8000 0x88000>;
+                       mbox-names = "txdb0", "txdb1",
+                               "rxdb0", "rxdb1";
+                       mboxes = <&mu2 2 0>, <&mu2 2 1>,
+                               <&mu2 3 0>, <&mu2 3 1>;
+                       memory-region = <&dsp_reserved>;
+                       status = "disabled";
+               };
        };
 };