Merge tag 'for-5.15/parisc' of git://git.kernel.org/pub/scm/linux/kernel/git/deller...

[linux-2.6-microblaze.git] / arch / arm64 / boot / dts / exynos / exynos5433.dtsi

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 18a912e..6a6f7dd 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -52,6 +52,38 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
+               cpu-map {
+                       cluster0 {
+                               core0 {
+                                       cpu = <&cpu0>;
+                               };
+                               core1 {
+                                       cpu = <&cpu1>;
+                               };
+                               core2 {
+                                       cpu = <&cpu2>;
+                               };
+                               core3 {
+                                       cpu = <&cpu3>;
+                               };
+                       };
+
+                       cluster1 {
+                               core0 {
+                                       cpu = <&cpu4>;
+                               };
+                               core1 {
+                                       cpu = <&cpu5>;
+                               };
+                               core2 {
+                                       cpu = <&cpu6>;
+                               };
+                               core3 {
+                                       cpu = <&cpu7>;
+                               };
+                       };
+               };
+
                cpu0: cpu@100 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
@@ -62,6 +94,13 @@
                        clock-names = "apolloclk";
                        operating-points-v2 = <&cluster_a53_opp_table>;
                        #cooling-cells = <2>;
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       next-level-cache = <&cluster_a53_l2>;
                };
 
                cpu1: cpu@101 {
@@ -72,6 +111,13 @@
                        clock-frequency = <1300000000>;
                        operating-points-v2 = <&cluster_a53_opp_table>;
                        #cooling-cells = <2>;
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       next-level-cache = <&cluster_a53_l2>;
                };
 
                cpu2: cpu@102 {
@@ -82,6 +128,13 @@
                        clock-frequency = <1300000000>;
                        operating-points-v2 = <&cluster_a53_opp_table>;
                        #cooling-cells = <2>;
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       next-level-cache = <&cluster_a53_l2>;
                };
 
                cpu3: cpu@103 {
@@ -92,6 +145,13 @@
                        clock-frequency = <1300000000>;
                        operating-points-v2 = <&cluster_a53_opp_table>;
                        #cooling-cells = <2>;
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       next-level-cache = <&cluster_a53_l2>;
                };
 
                cpu4: cpu@0 {
@@ -104,6 +164,13 @@
                        clock-names = "atlasclk";
                        operating-points-v2 = <&cluster_a57_opp_table>;
                        #cooling-cells = <2>;
+                       i-cache-size = <0xc000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&cluster_a57_l2>;
                };
 
                cpu5: cpu@1 {
@@ -114,6 +181,13 @@
                        clock-frequency = <1900000000>;
                        operating-points-v2 = <&cluster_a57_opp_table>;
                        #cooling-cells = <2>;
+                       i-cache-size = <0xc000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&cluster_a57_l2>;
                };
 
                cpu6: cpu@2 {
@@ -124,6 +198,13 @@
                        clock-frequency = <1900000000>;
                        operating-points-v2 = <&cluster_a57_opp_table>;
                        #cooling-cells = <2>;
+                       i-cache-size = <0xc000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&cluster_a57_l2>;
                };
 
                cpu7: cpu@3 {
@@ -134,6 +215,27 @@
                        clock-frequency = <1900000000>;
                        operating-points-v2 = <&cluster_a57_opp_table>;
                        #cooling-cells = <2>;
+                       i-cache-size = <0xc000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&cluster_a57_l2>;
+               };
+
+               cluster_a57_l2: l2-cache0 {
+                       compatible = "cache";
+                       cache-size = <0x200000>;
+                       cache-line-size = <64>;
+                       cache-sets = <2048>;
+               };
+
+               cluster_a53_l2: l2-cache1 {
+                       compatible = "cache";
+                       cache-size = <0x40000>;
+                       cache-line-size = <64>;
+                       cache-sets = <256>;
                };
        };