ARM: zynq: use physical cpuid in zynq_slcr_cpu_stop/start

[linux-2.6-microblaze.git] / arch / arm / mach-zynq / platsmp.c

diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c
index a10085b..68ec303 100644 (file)
--- a/arch/arm/mach-zynq/platsmp.c
+++ b/arch/arm/mach-zynq/platsmp.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <linux/irqchip/arm-gic.h>
 #include "common.h"
@@ -30,6 +31,7 @@ int zynq_cpun_start(u32 address, int cpu)
 {
        u32 trampoline_code_size = &zynq_secondary_trampoline_end -
                                                &zynq_secondary_trampoline;
+       u32 phy_cpuid = cpu_logical_map(cpu);
 
        /* MS: Expectation that SLCR are directly map and accessible */
        /* Not possible to jump to non aligned address */
@@ -39,7 +41,7 @@ int zynq_cpun_start(u32 address, int cpu)
                u32 trampoline_size = &zynq_secondary_trampoline_jump -
                                                &zynq_secondary_trampoline;
 
-               zynq_slcr_cpu_stop(cpu);
+               zynq_slcr_cpu_stop(phy_cpuid);
                if (address) {
                        if (__pa(PAGE_OFFSET)) {
                                zero = ioremap(0, trampoline_code_size);
@@ -68,7 +70,7 @@ int zynq_cpun_start(u32 address, int cpu)
                        if (__pa(PAGE_OFFSET))
                                iounmap(zero);
                }
-               zynq_slcr_cpu_start(cpu);
+               zynq_slcr_cpu_start(phy_cpuid);
 
                return 0;
        }