#include <linux/cpu.h>
#include <linux/pci.h>
#include <linux/sched_clock.h>
+#include <linux/soc/ixp4xx/cpu.h>
#include <linux/irqchip/irq-ixp4xx.h>
#include <linux/platform_data/timer-ixp4xx.h>
#include <linux/dma-map-ops.h>
#include <mach/udc.h>
#include <mach/hardware.h>
-#include <mach/io.h>
#include <linux/uaccess.h>
#include <asm/page.h>
#include <asm/exception.h>
#include "irqs.h"
+u32 ixp4xx_read_feature_bits(void)
+{
+ u32 val = ~__raw_readl(IXP4XX_EXP_CFG2);
+
+ if (cpu_is_ixp42x_rev_a0())
+ return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
+ IXP4XX_FEATURE_AES);
+ if (cpu_is_ixp42x())
+ return val & IXP42X_FEATURE_MASK;
+ if (cpu_is_ixp43x())
+ return val & IXP43X_FEATURE_MASK;
+ return val & IXP46X_FEATURE_MASK;
+}
+EXPORT_SYMBOL(ixp4xx_read_feature_bits);
+
+void ixp4xx_write_feature_bits(u32 value)
+{
+ __raw_writel(~value, IXP4XX_EXP_CFG2);
+}
+EXPORT_SYMBOL(ixp4xx_write_feature_bits);
+
#define IXP4XX_TIMER_FREQ 66666000
/*************************************************************************
}
};
+/* A single 32-bit register on IXP46x */
+#define IXP4XX_HWRANDOM_BASE_PHYS 0x70002100
+
+static struct resource ixp46x_hwrandom_resource[] = {
+ {
+ .start = IXP4XX_HWRANDOM_BASE_PHYS,
+ .end = IXP4XX_HWRANDOM_BASE_PHYS + 0x3,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device ixp46x_hwrandom_device = {
+ .name = "ixp4xx-hwrandom",
+ .id = -1,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .resource = ixp46x_hwrandom_resource,
+ .num_resources = ARRAY_SIZE(ixp46x_hwrandom_resource),
+};
+
/*
* I2C controller. The IXP46x uses the same block as the IOP3xx, so
* we just use the same device name.
};
static struct platform_device *ixp46x_devices[] __initdata = {
- &ixp46x_i2c_controller
+ &ixp46x_hwrandom_device,
+ &ixp46x_i2c_controller,
};
unsigned long ixp4xx_exp_bus_size;