ARM: tegra: cardhu: Support CPU frequency and voltage scaling on all board variants
[linux-2.6-microblaze.git] / arch / arm / boot / dts / tegra30-cardhu.dtsi
index dab9989..42ea949 100644 (file)
@@ -1,6 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0
 #include <dt-bindings/input/input.h>
 #include "tegra30.dtsi"
+#include "tegra30-cpu-opp.dtsi"
+#include "tegra30-cpu-opp-microvolt.dtsi"
 
 /**
  * This file contains common DT entry for all fab version of Cardhu.
 
                                vddctrl_reg: vddctrl {
                                        regulator-name = "vdd_cpu,vdd_sys";
-                                       regulator-min-microvolt = <1000000>;
-                                       regulator-max-microvolt = <1000000>;
+                                       regulator-min-microvolt = <800000>;
+                                       regulator-max-microvolt = <1250000>;
+                                       regulator-coupled-with = <&vdd_core>;
+                                       regulator-coupled-max-spread = <300000>;
+                                       regulator-max-step-microvolt = <100000>;
                                        regulator-always-on;
+
+                                       nvidia,tegra-cpu-regulator;
                                };
 
                                vio_reg: vio {
                        interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
                };
 
-               tps62361@60 {
+               vdd_core: tps62361@60 {
                        compatible = "ti,tps62361";
                        reg = <0x60>;
 
                        regulator-name = "tps62361-vout";
                        regulator-min-microvolt = <500000>;
                        regulator-max-microvolt = <1500000>;
+                       regulator-coupled-with = <&vddctrl_reg>;
+                       regulator-coupled-max-spread = <300000>;
+                       regulator-max-step-microvolt = <100000>;
                        regulator-boot-on;
                        regulator-always-on;
                        ti,vsel0-state-high;
                        ti,vsel1-state-high;
+
+                       nvidia,tegra-core-regulator;
                };
        };
 
                #clock-cells = <0>;
        };
 
+       cpus {
+               cpu0: cpu@0 {
+                       cpu-supply = <&vddctrl_reg>;
+                       operating-points-v2 = <&cpu0_opp_table>;
+               };
+
+               cpu1: cpu@1 {
+                       cpu-supply = <&vddctrl_reg>;
+                       operating-points-v2 = <&cpu0_opp_table>;
+               };
+
+               cpu2: cpu@2 {
+                       cpu-supply = <&vddctrl_reg>;
+                       operating-points-v2 = <&cpu0_opp_table>;
+               };
+
+               cpu3: cpu@3 {
+                       cpu-supply = <&vddctrl_reg>;
+                       operating-points-v2 = <&cpu0_opp_table>;
+               };
+       };
+
        panel: panel {
                compatible = "chunghwa,claa101wb01";
                ddc-i2c-bus = <&panelddc>;