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Merge tag 'arc-5.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
[linux-2.6-microblaze.git]
/
arch
/
arm
/
boot
/
dts
/
stih410-clock.dtsi
diff --git
a/arch/arm/boot/dts/stih410-clock.dtsi
b/arch/arm/boot/dts/stih410-clock.dtsi
index
3aeabdd
..
6b0e6d4
100644
(file)
--- a/
arch/arm/boot/dts/stih410-clock.dtsi
+++ b/
arch/arm/boot/dts/stih410-clock.dtsi
@@
-93,12
+93,6
@@
reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>;
reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
- "clk-s-c0-fs0-ch1",
- "clk-s-c0-fs0-ch2",
- "clk-s-c0-fs0-ch3";
- clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
};
clk_s_c0: clockgen-c@9103000 {
};
clk_s_c0: clockgen-c@9103000 {
@@
-150,15
+144,10
@@
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs
-d0
";
reg = <0x9104000 0x1000>;
clocks = <&clk_sysin>;
reg = <0x9104000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
- "clk-s-d0-fs0-ch1",
- "clk-s-d0-fs0-ch2",
- "clk-s-d0-fs0-ch3";
};
clockgen-d0@9104000 {
};
clockgen-d0@9104000 {
@@
-179,15
+168,10
@@
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs
-d2
";
reg = <0x9106000 0x1000>;
clocks = <&clk_sysin>;
reg = <0x9106000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
- "clk-s-d2-fs0-ch1",
- "clk-s-d2-fs0-ch2",
- "clk-s-d2-fs0-ch3";
};
clockgen-d2@9106000 {
};
clockgen-d2@9106000 {
@@
-210,15
+194,10
@@
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs
-d3
";
reg = <0x9107000 0x1000>;
clocks = <&clk_sysin>;
reg = <0x9107000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
- "clk-s-d3-fs0-ch1",
- "clk-s-d3-fs0-ch2",
- "clk-s-d3-fs0-ch3";
};
clockgen-d3@9107000 {
};
clockgen-d3@9107000 {