Merge tag 'fscache-next-20210829' of git://git.kernel.org/pub/scm/linux/kernel/git...

[linux-2.6-microblaze.git] / arch / arm / boot / dts / stih410-clock.dtsi

diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
index 04b0d70..6b0e6d4 100644 (file)
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -39,8 +39,6 @@
                                compatible = "st,stih407-clkgen-plla9";
 
                                clocks = <&clk_sysin>;
-
-                               clock-output-names = "clockgen-a9-pll-odf";
                        };
                };
 
@@ -74,12 +72,9 @@
 
                        clk_s_a0_pll: clk-s-a0-pll {
                                #clock-cells = <1>;
-                               compatible = "st,clkgen-pll0";
+                               compatible = "st,clkgen-pll0-a0";
 
                                clocks = <&clk_sysin>;
-
-                               clock-output-names = "clk-s-a0-pll-ofd-0";
-                               clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
                        };
 
                        clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -98,12 +93,6 @@
                        reg = <0x9103000 0x1000>;
 
                        clocks = <&clk_sysin>;
-
-                       clock-output-names = "clk-s-c0-fs0-ch0",
-                                            "clk-s-c0-fs0-ch1",
-                                            "clk-s-c0-fs0-ch2",
-                                            "clk-s-c0-fs0-ch3";
-                       clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
                };
 
                clk_s_c0: clockgen-c@9103000 {
@@ -112,21 +101,16 @@
 
                        clk_s_c0_pll0: clk-s-c0-pll0 {
                                #clock-cells = <1>;
-                               compatible = "st,clkgen-pll0";
+                               compatible = "st,clkgen-pll0-c0";
 
                                clocks = <&clk_sysin>;
-
-                               clock-output-names = "clk-s-c0-pll0-odf-0";
-                               clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
                        };
 
                        clk_s_c0_pll1: clk-s-c0-pll1 {
                                #clock-cells = <1>;
-                               compatible = "st,clkgen-pll1";
+                               compatible = "st,clkgen-pll1-c0";
 
                                clocks = <&clk_sysin>;
-
-                               clock-output-names = "clk-s-c0-pll1-odf-0";
                        };
 
                        clk_s_c0_flexgen: clk-s-c0-flexgen {
@@ -160,15 +144,10 @@
 
                clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
                        #clock-cells = <1>;
-                       compatible = "st,quadfs";
+                       compatible = "st,quadfs-d0";
                        reg = <0x9104000 0x1000>;
 
                        clocks = <&clk_sysin>;
-
-                       clock-output-names = "clk-s-d0-fs0-ch0",
-                                            "clk-s-d0-fs0-ch1",
-                                            "clk-s-d0-fs0-ch2",
-                                            "clk-s-d0-fs0-ch3";
                };
 
                clockgen-d0@9104000 {
@@ -189,15 +168,10 @@
 
                clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
                        #clock-cells = <1>;
-                       compatible = "st,quadfs";
+                       compatible = "st,quadfs-d2";
                        reg = <0x9106000 0x1000>;
 
                        clocks = <&clk_sysin>;
-
-                       clock-output-names = "clk-s-d2-fs0-ch0",
-                                            "clk-s-d2-fs0-ch1",
-                                            "clk-s-d2-fs0-ch2",
-                                            "clk-s-d2-fs0-ch3";
                };
 
                clockgen-d2@9106000 {
@@ -220,15 +194,10 @@
 
                clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
                        #clock-cells = <1>;
-                       compatible = "st,quadfs";
+                       compatible = "st,quadfs-d3";
                        reg = <0x9107000 0x1000>;
 
                        clocks = <&clk_sysin>;
-
-                       clock-output-names = "clk-s-d3-fs0-ch0",
-                                            "clk-s-d3-fs0-ch1",
-                                            "clk-s-d3-fs0-ch2",
-                                            "clk-s-d3-fs0-ch3";
                };
 
                clockgen-d3@9107000 {