Merge commit '81fd23e2b3ccf71c807e671444e8accaba98ca53' of https://git.pengutronix...

[linux-2.6-microblaze.git] / arch / arm / boot / dts / rk322x.dtsi

diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 208f212..75af99c 100644 (file)
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/clock/rk3228-cru.h>
 #include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/power/rk3228-power.h>
 
 / {
        #address-cells = <1>;
@@ -190,7 +191,65 @@
                        status = "disabled";
                };
 
-               u2phy0: usb2-phy@760 {
+               power: power-controller {
+                       compatible = "rockchip,rk3228-power-controller";
+                       #power-domain-cells = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       power-domain@RK3228_PD_VIO {
+                               reg = <RK3228_PD_VIO>;
+                               clocks = <&cru ACLK_HDCP>,
+                                        <&cru SCLK_HDCP>,
+                                        <&cru ACLK_IEP>,
+                                        <&cru HCLK_IEP>,
+                                        <&cru ACLK_RGA>,
+                                        <&cru HCLK_RGA>,
+                                        <&cru SCLK_RGA>;
+                               pm_qos = <&qos_hdcp>,
+                                        <&qos_iep>,
+                                        <&qos_rga_r>,
+                                        <&qos_rga_w>;
+                               #power-domain-cells = <0>;
+                       };
+
+                       power-domain@RK3228_PD_VOP {
+                               reg = <RK3228_PD_VOP>;
+                               clocks =<&cru ACLK_VOP>,
+                                       <&cru DCLK_VOP>,
+                                       <&cru HCLK_VOP>;
+                               pm_qos = <&qos_vop>;
+                               #power-domain-cells = <0>;
+                       };
+
+                       power-domain@RK3228_PD_VPU {
+                               reg = <RK3228_PD_VPU>;
+                               clocks = <&cru ACLK_VPU>,
+                                        <&cru HCLK_VPU>;
+                               pm_qos = <&qos_vpu>;
+                               #power-domain-cells = <0>;
+                       };
+
+                       power-domain@RK3228_PD_RKVDEC {
+                               reg = <RK3228_PD_RKVDEC>;
+                               clocks = <&cru ACLK_RKVDEC>,
+                                        <&cru HCLK_RKVDEC>,
+                                        <&cru SCLK_VDEC_CABAC>,
+                                        <&cru SCLK_VDEC_CORE>;
+                               pm_qos = <&qos_rkvdec_r>,
+                                        <&qos_rkvdec_w>;
+                               #power-domain-cells = <0>;
+                       };
+
+                       power-domain@RK3228_PD_GPU {
+                               reg = <RK3228_PD_GPU>;
+                               clocks = <&cru ACLK_GPU>;
+                               pm_qos = <&qos_gpu>;
+                               #power-domain-cells = <0>;
+                       };
+               };
+
+               u2phy0: usb2phy@760 {
                        compatible = "rockchip,rk3228-usb2phy";
                        reg = <0x0760 0x0c>;
                        clocks = <&cru SCLK_OTGPHY0>;
@@ -217,7 +276,7 @@
                        };
                };
 
-               u2phy1: usb2-phy@800 {
+               u2phy1: usb2phy@800 {
                        compatible = "rockchip,rk3228-usb2phy";
                        reg = <0x0800 0x0c>;
                        clocks = <&cru SCLK_OTGPHY1>;
@@ -379,7 +438,6 @@
                reg = <0x110b0000 0x10>;
                #pwm-cells = <3>;
                clocks = <&cru PCLK_PWM>;
-               clock-names = "pwm";
                pinctrl-names = "default";
                pinctrl-0 = <&pwm0_pin>;
                status = "disabled";
@@ -390,7 +448,6 @@
                reg = <0x110b0010 0x10>;
                #pwm-cells = <3>;
                clocks = <&cru PCLK_PWM>;
-               clock-names = "pwm";
                pinctrl-names = "default";
                pinctrl-0 = <&pwm1_pin>;
                status = "disabled";
@@ -401,7 +458,6 @@
                reg = <0x110b0020 0x10>;
                #pwm-cells = <3>;
                clocks = <&cru PCLK_PWM>;
-               clock-names = "pwm";
                pinctrl-names = "default";
                pinctrl-0 = <&pwm2_pin>;
                status = "disabled";
@@ -412,7 +468,6 @@
                reg = <0x110b0030 0x10>;
                #pwm-cells = <2>;
                clocks = <&cru PCLK_PWM>;
-               clock-names = "pwm";
                pinctrl-names = "default";
                pinctrl-0 = <&pwm3_pin>;
                status = "disabled";
@@ -517,7 +572,7 @@
                pinctrl-0 = <&otp_pin>;
                pinctrl-1 = <&otp_out>;
                pinctrl-2 = <&otp_pin>;
-               #thermal-sensor-cells = <0>;
+               #thermal-sensor-cells = <1>;
                rockchip,hw-tshut-temp = <95000>;
                status = "disabled";
        };
@@ -550,30 +605,54 @@
                                  "ppmmu1";
                clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
                clock-names = "bus", "core";
+               power-domains = <&power RK3228_PD_GPU>;
                resets = <&cru SRST_GPU_A>;
                status = "disabled";
        };
 
+       vpu: video-codec@20020000 {
+               compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu";
+               reg = <0x20020000 0x800>;
+               interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "vepu", "vdpu";
+               clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+               clock-names = "aclk", "hclk";
+               iommus = <&vpu_mmu>;
+               power-domains = <&power RK3228_PD_VPU>;
+       };
+
        vpu_mmu: iommu@20020800 {
                compatible = "rockchip,iommu";
                reg = <0x20020800 0x100>;
                interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-               interrupt-names = "vpu_mmu";
                clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
                clock-names = "aclk", "iface";
-               iommu-cells = <0>;
-               status = "disabled";
+               power-domains = <&power RK3228_PD_VPU>;
+               #iommu-cells = <0>;
+       };
+
+       vdec: video-codec@20030000 {
+               compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec";
+               reg = <0x20030000 0x480>;
+               interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
+                        <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
+               clock-names = "axi", "ahb", "cabac", "core";
+               assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
+               assigned-clock-rates = <300000000>, <300000000>;
+               iommus = <&vdec_mmu>;
+               power-domains = <&power RK3228_PD_RKVDEC>;
        };
 
        vdec_mmu: iommu@20030480 {
                compatible = "rockchip,iommu";
                reg = <0x20030480 0x40>, <0x200304c0 0x40>;
                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-               interrupt-names = "vdec_mmu";
                clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
                clock-names = "aclk", "iface";
-               iommu-cells = <0>;
-               status = "disabled";
+               power-domains = <&power RK3228_PD_RKVDEC>;
+               #iommu-cells = <0>;
        };
 
        vop: vop@20050000 {
@@ -585,6 +664,7 @@
                resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
                reset-names = "axi", "ahb", "dclk";
                iommus = <&vop_mmu>;
+               power-domains = <&power RK3228_PD_VOP>;
                status = "disabled";
 
                vop_out: port {
@@ -602,9 +682,9 @@
                compatible = "rockchip,iommu";
                reg = <0x20053f00 0x100>;
                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-               interrupt-names = "vop_mmu";
                clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
                clock-names = "aclk", "iface";
+               power-domains = <&power RK3228_PD_VOP>;
                #iommu-cells = <0>;
                status = "disabled";
        };
@@ -615,6 +695,7 @@
                interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
                clock-names = "aclk", "hclk", "sclk";
+               power-domains = <&power RK3228_PD_VIO>;
                resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
                reset-names = "core", "axi", "ahb";
        };
@@ -623,10 +704,10 @@
                compatible = "rockchip,iommu";
                reg = <0x20070800 0x100>;
                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-               interrupt-names = "iep_mmu";
                clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
                clock-names = "aclk", "iface";
-               iommu-cells = <0>;
+               power-domains = <&power RK3228_PD_VIO>;
+               #iommu-cells = <0>;
                status = "disabled";
        };
 
@@ -800,6 +881,51 @@
                status = "disabled";
        };
 
+       qos_iep: qos@31030080 {
+               compatible = "rockchip,rk3228-qos", "syscon";
+               reg = <0x31030080 0x20>;
+       };
+
+       qos_rga_w: qos@31030100 {
+               compatible = "rockchip,rk3228-qos", "syscon";
+               reg = <0x31030100 0x20>;
+       };
+
+       qos_hdcp: qos@31030180 {
+               compatible = "rockchip,rk3228-qos", "syscon";
+               reg = <0x31030180 0x20>;
+       };
+
+       qos_rga_r: qos@31030200 {
+               compatible = "rockchip,rk3228-qos", "syscon";
+               reg = <0x31030200 0x20>;
+       };
+
+       qos_vpu: qos@31040000 {
+               compatible = "rockchip,rk3228-qos", "syscon";
+               reg = <0x31040000 0x20>;
+       };
+
+       qos_gpu: qos@31050000 {
+               compatible = "rockchip,rk3228-qos", "syscon";
+               reg = <0x31050000 0x20>;
+       };
+
+       qos_vop: qos@31060000 {
+               compatible = "rockchip,rk3228-qos", "syscon";
+               reg = <0x31060000 0x20>;
+       };
+
+       qos_rkvdec_r: qos@31070000 {
+               compatible = "rockchip,rk3228-qos", "syscon";
+               reg = <0x31070000 0x20>;
+       };
+
+       qos_rkvdec_w: qos@31070080 {
+               compatible = "rockchip,rk3228-qos", "syscon";
+               reg = <0x31070080 0x20>;
+       };
+
        gic: interrupt-controller@32010000 {
                compatible = "arm,gic-400";
                interrupt-controller;