Merge commit '81fd23e2b3ccf71c807e671444e8accaba98ca53' of https://git.pengutronix...

[linux-2.6-microblaze.git] / arch / arm / boot / dts / rk3188.dtsi

diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 2298a8d..793a1b9 100644 (file)
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -150,16 +150,16 @@
                compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
                reg = <0x2000e000 0x20>;
                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>;
-               clock-names = "timer", "pclk";
+               clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>;
+               clock-names = "pclk", "timer";
        };
 
        timer6: timer@200380a0 {
                compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
                reg = <0x200380a0 0x20>;
                interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>;
-               clock-names = "timer", "pclk";
+               clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>;
+               clock-names = "pclk", "timer";
        };
 
        i2s0: i2s@1011a000 {
@@ -214,30 +214,6 @@
                };
        };
 
-       usbphy: phy {
-               compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
-               rockchip,grf = <&grf>;
-               #address-cells = <1>;
-               #size-cells = <0>;
-               status = "disabled";
-
-               usbphy0: usb-phy@10c {
-                       #phy-cells = <0>;
-                       reg = <0x10c>;
-                       clocks = <&cru SCLK_OTGPHY0>;
-                       clock-names = "phyclk";
-                       #clock-cells = <0>;
-               };
-
-               usbphy1: usb-phy@11c {
-                       #phy-cells = <0>;
-                       reg = <0x11c>;
-                       clocks = <&cru SCLK_OTGPHY1>;
-                       clock-names = "phyclk";
-                       #clock-cells = <0>;
-               };
-       };
-
        pinctrl: pinctrl {
                compatible = "rockchip,rk3188-pinctrl";
                rockchip,grf = <&grf>;
@@ -662,6 +638,34 @@
        power-domains = <&power RK3188_PD_GPU>;
 };
 
+&grf{
+       compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";
+
+       usbphy: usbphy {
+               compatible = "rockchip,rk3188-usb-phy",
+                            "rockchip,rk3288-usb-phy";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+
+               usbphy0: usb-phy@10c {
+                       reg = <0x10c>;
+                       clocks = <&cru SCLK_OTGPHY0>;
+                       clock-names = "phyclk";
+                       #clock-cells = <0>;
+                       #phy-cells = <0>;
+               };
+
+               usbphy1: usb-phy@11c {
+                       reg = <0x11c>;
+                       clocks = <&cru SCLK_OTGPHY1>;
+                       clock-names = "phyclk";
+                       #clock-cells = <0>;
+                       #phy-cells = <0>;
+               };
+       };
+};
+
 &i2c0 {
        compatible = "rockchip,rk3188-i2c";
        pinctrl-names = "default";
@@ -699,7 +703,7 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
-               pd_vio@RK3188_PD_VIO {
+               power-domain@RK3188_PD_VIO {
                        reg = <RK3188_PD_VIO>;
                        clocks = <&cru ACLK_LCDC0>,
                                 <&cru ACLK_LCDC1>,
@@ -719,21 +723,24 @@
                                 <&qos_cif0>,
                                 <&qos_ipp>,
                                 <&qos_rga>;
+                       #power-domain-cells = <0>;
                };
 
-               pd_video@RK3188_PD_VIDEO {
+               power-domain@RK3188_PD_VIDEO {
                        reg = <RK3188_PD_VIDEO>;
                        clocks = <&cru ACLK_VDPU>,
                                 <&cru ACLK_VEPU>,
                                 <&cru HCLK_VDPU>,
                                 <&cru HCLK_VEPU>;
                        pm_qos = <&qos_vpu>;
+                       #power-domain-cells = <0>;
                };
 
-               pd_gpu@RK3188_PD_GPU {
+               power-domain@RK3188_PD_GPU {
                        reg = <RK3188_PD_GPU>;
                        clocks = <&cru ACLK_GPU>;
                        pm_qos = <&qos_gpu>;
+                       #power-domain-cells = <0>;
                };
        };
 };
@@ -794,6 +801,11 @@
        pinctrl-0 = <&uart3_xfer>;
 };
 
+&vpu {
+       compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu";
+       power-domains = <&power RK3188_PD_VIDEO>;
+};
+
 &wdt {
        compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
 };