Merge commit '81fd23e2b3ccf71c807e671444e8accaba98ca53' of https://git.pengutronix...

[linux-2.6-microblaze.git] / arch / arm / boot / dts / r8a7790.dtsi

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index de29394..ed6dd4f 100644 (file)
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -69,7 +69,6 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-               enable-method = "renesas,apmu";
 
                cpu0: cpu@0 {
                        device_type = "cpu";
@@ -78,6 +77,7 @@
                        clock-frequency = <1300000000>;
                        clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
                        power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
                        voltage-tolerance = <1>; /* 1% */
@@ -99,6 +99,7 @@
                        clock-frequency = <1300000000>;
                        clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
                        power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
                        voltage-tolerance = <1>; /* 1% */
@@ -120,6 +121,7 @@
                        clock-frequency = <1300000000>;
                        clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
                        power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
                        voltage-tolerance = <1>; /* 1% */
@@ -141,6 +143,7 @@
                        clock-frequency = <1300000000>;
                        clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
                        power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
                        voltage-tolerance = <1>; /* 1% */
@@ -162,6 +165,7 @@
                        clock-frequency = <780000000>;
                        clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
                        power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA7>;
                        capacity-dmips-mhz = <539>;
                };
@@ -173,6 +177,7 @@
                        clock-frequency = <780000000>;
                        clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
                        power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA7>;
                        capacity-dmips-mhz = <539>;
                };
@@ -184,6 +189,7 @@
                        clock-frequency = <780000000>;
                        clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
                        power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA7>;
                        capacity-dmips-mhz = <539>;
                };
@@ -195,6 +201,7 @@
                        clock-frequency = <780000000>;
                        clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
                        power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA7>;
                        capacity-dmips-mhz = <539>;
                };
@@ -768,6 +775,7 @@
                        reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
                        interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 812>;
+                       clock-names = "fck";
                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                        resets = <&cpg 812>;
                        #address-cells = <1>;