};
soc {
- bus@50000000 {
- flash@0 {
+ bus@c4000000 {
+ flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
+ /* Enable writes on the expansion bus */
+ intel,ixp4xx-eb-write-enable = <1>;
/*
* 32 MB of Flash in 0x20000 byte blocks
- * mapped in at CS0.
+ * mapped in at CS0 and CS1
*/
- reg = <0x00000000 0x2000000>;
+ reg = <0 0x00000000 0x2000000>;
partitions {
compatible = "redboot-fis";
fis-index-block = <0xff>;
};
};
+ ide@3,0 {
+ compatible = "intel,ixp4xx-compact-flash";
+ /*
+ * Set up expansion bus config to a really slow timing.
+ * The CF driver will dynamically reconfigure these timings
+ * depending on selected PIO mode (0-4).
+ */
+ intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
+ intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
+ intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
+ intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
+ intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
+ intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
+ intel,ixp4xx-eb-byte-access-on-halfword = <1>;
+ intel,ixp4xx-eb-mux-address-and-data = <0>;
+ intel,ixp4xx-eb-ahb-split-transfers = <0>;
+ intel,ixp4xx-eb-write-enable = <1>;
+ intel,ixp4xx-eb-byte-access = <1>;
+ /* First register set is CMD second is CTL */
+ reg = <3 0xe00000 0x40000>, <3 0xe40000 0x40000>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <12 IRQ_TYPE_EDGE_RISING>;
+ };
};
pci@c0000000 {
*/
interrupt-map =
/* IDSEL 1 */
- <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
- <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
- <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
- <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
+ <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
+ <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
+ <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
+ <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
/* IDSEL 2 */
- <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
- <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
- <0x1000 0 0 3 &gpio0 8 3>, /* INT C on slot 2 is irq 8 */
- <0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */
+ <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
+ <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
+ <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
+ <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
/* IDSEL 3 */
- <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
- <0x1800 0 0 2 &gpio0 8 3>, /* INT B on slot 3 is irq 8 */
- <0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */
- <0x1800 0 0 4 &gpio0 10 3>, /* INT D on slot 3 is irq 10 */
+ <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
+ <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
+ <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
+ <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
/* IDSEL 4 */
- <0x2000 0 0 1 &gpio0 8 3>, /* INT A on slot 3 is irq 8 */
- <0x2000 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
- <0x2000 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
- <0x2000 0 0 4 &gpio0 9 3>, /* INT D on slot 3 is irq 9 */
+ <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
+ <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
+ <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
+ <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 9 */
/* IDSEL 6 */
- <0x3000 0 0 1 &gpio0 10 3>, /* INT A on slot 3 is irq 10 */
- <0x3000 0 0 2 &gpio0 9 3>, /* INT B on slot 3 is irq 9 */
- <0x3000 0 0 3 &gpio0 8 3>, /* INT C on slot 3 is irq 8 */
- <0x3000 0 0 4 &gpio0 11 3>, /* INT D on slot 3 is irq 11 */
+ <0x3000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 10 */
+ <0x3000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 9 */
+ <0x3000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 8 */
+ <0x3000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 11 */
/* IDSEL 15 */
- <0x7800 0 0 1 &gpio0 8 3>, /* INT A on slot 3 is irq 8 */
- <0x7800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
- <0x7800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
- <0x7800 0 0 4 &gpio0 9 3>; /* INT D on slot 3 is irq 9 */
+ <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
+ <0x7800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
+ <0x7800 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
+ <0x7800 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 9 */
};
ethernet@c800a000 {
projects / linux-2.6-microblaze.git / blobdiff