soc {
compatible = "ti,omap-infra";
- mpu {
- compatible = "ti,omap4-mpu";
- ti,hwmods = "mpu";
- pm-sram = <&pm_sram_code
- &pm_sram_data>;
- };
};
gic: interrupt-controller@48241000 {
};
ocp@44000000 {
- compatible = "ti,am4372-l3-noc", "simple-bus";
+ compatible = "simple-pm-bus";
+ power-domains = <&prm_per>;
+ clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- ti,hwmods = "l3_main";
ti,no-idle;
- reg = <0x44000000 0x400000
- 0x44800000 0x400000>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+ l3-noc@44000000 {
+ compatible = "ti,am4372-l3-noc";
+ reg = <0x44000000 0x400000>,
+ <0x44800000 0x400000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ };
l4_wkup: interconnect@44c00000 {
- wkup_m3: wkup_m3@100000 {
- compatible = "ti,am4372-wkup-m3";
- reg = <0x100000 0x4000>,
- <0x180000 0x2000>;
- reg-names = "umem", "dmem";
- ti,hwmods = "wkup_m3";
- ti,pm-firmware = "am335x-pm-firmware.elf";
- };
};
l4_per: interconnect@48000000 {
};
l4_fast: interconnect@4a000000 {
};
- emif: emif@4c000000 {
- compatible = "ti,emif-am4372";
- reg = <0x4c000000 0x1000000>;
- ti,hwmods = "emif";
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ target-module@4c000000 {
+ compatible = "ti,sysc-omap4-simple", "ti,sysc";
+ reg = <0x4c000000 0x4>;
+ reg-names = "rev";
+ clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>;
+ clock-names = "fck";
ti,no-idle;
- sram = <&pm_sram_code
- &pm_sram_data>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4c000000 0x1000000>;
+
+ emif: emif@0 {
+ compatible = "ti,emif-am4372";
+ reg = <0 0x1000000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ sram = <&pm_sram_code
+ &pm_sram_data>;
+ };
};
target-module@49000000 {
};
};
- ocmcram: sram@40300000 {
- compatible = "mmio-sram";
- reg = <0x40300000 0x40000>; /* 256k */
- ranges = <0x0 0x40300000 0x40000>;
+ target-module@40300000 {
+ compatible = "ti,sysc-omap4-simple", "ti,sysc";
+ clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>;
+ clock-names = "fck";
+ ti,no-idle;
#address-cells = <1>;
#size-cells = <1>;
+ ranges = <0 0x40300000 0x40000>;
- pm_sram_code: pm-code-sram@0 {
- compatible = "ti,sram";
- reg = <0x0 0x1000>;
- protect-exec;
- };
+ ocmcram: sram@0 {
+ compatible = "mmio-sram";
+ reg = <0 0x40000>; /* 256k */
+ ranges = <0 0 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
- pm_sram_data: pm-data-sram@1000 {
- compatible = "ti,sram";
- reg = <0x1000 0x1000>;
- pool;
+ pm_sram_code: pm-code-sram@0 {
+ compatible = "ti,sram";
+ reg = <0x0 0x1000>;
+ protect-exec;
+ };
+
+ pm_sram_data: pm-data-sram@1000 {
+ compatible = "ti,sram";
+ reg = <0x1000 0x1000>;
+ pool;
+ };
};
};
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
+ clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>,
+ <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
+ clock-names = "fck", "ick";
timer@0 {
assigned-clocks = <&timer1_fck>;
assigned-clock-parents = <&sys_clkin_ck>;
&timer2_target {
ti,no-reset-on-init;
ti,no-idle;
+ clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>,
+ <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>;
+ clock-names = "fck", "ick";
timer@0 {
assigned-clocks = <&timer2_fck>;
assigned-clock-parents = <&sys_clkin_ck>;