target-module@4b000000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
- clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>;
+ clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>;
clock-names = "fck";
+ ti,no-idle;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b000000 0x1000000>;
- pmu@0 {
- compatible = "arm,cortex-a8-pmu";
- interrupts = <3>;
- reg = <0 0x1000000>;
- ti,hwmods = "debugss";
+ target-module@140000 {
+ compatible = "ti,sysc-omap4-simple", "ti,sysc";
+ clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x140000 0xec0000>;
+
+ pmu@0 {
+ compatible = "arm,cortex-a8-pmu";
+ interrupts = <3>;
+ };
};
};
*/
soc {
compatible = "ti,omap-infra";
- mpu {
- compatible = "ti,omap3-mpu";
- ti,hwmods = "mpu";
- pm-sram = <&pm_sram_code
- &pm_sram_data>;
- };
};
/*
* the whole bus hierarchy.
*/
ocp: ocp {
- compatible = "simple-bus";
+ compatible = "simple-pm-bus";
+ power-domains = <&prm_per>;
+ clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- ti,hwmods = "l3_main";
l4_wkup: interconnect@44c00000 {
};