ARC: mm: remove tlb paranoid code

[linux-2.6-microblaze.git] / arch / arc / mm / tlbex.S

diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index bcd2909..0b4bb62 100644 (file)
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -93,11 +93,6 @@ ex_saved_reg1:
        st_s  r1, [r0, 4]
        st_s  r2, [r0, 8]
        st_s  r3, [r0, 12]
-
-       ; VERIFY if the ASID in MMU-PID Reg is same as
-       ; one in Linux data structures
-
-       tlb_paranoid_check_asm
 .endm
 
 .macro TLBMISS_RESTORE_REGS
@@ -146,51 +141,6 @@ ex_saved_reg1:
 
 #endif
 
-;============================================================================
-;  Troubleshooting Stuff
-;============================================================================
-
-; Linux keeps ASID (Address Space ID) in task->active_mm->context.asid
-; When Creating TLB Entries, instead of doing 3 dependent loads from memory,
-; we use the MMU PID Reg to get current ASID.
-; In bizzare scenrios SW and HW ASID can get out-of-sync which is trouble.
-; So we try to detect this in TLB Mis shandler
-
-.macro tlb_paranoid_check_asm
-
-#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
-
-       GET_CURR_TASK_ON_CPU  r3
-       ld r0, [r3, TASK_ACT_MM]
-       ld r0, [r0, MM_CTXT+MM_CTXT_ASID]
-       breq r0, 0, 55f ; Error if no ASID allocated
-
-       lr r1, [ARC_REG_PID]
-       and r1, r1, 0xFF
-
-       and r2, r0, 0xFF        ; MMU PID bits only for comparison
-       breq r1, r2, 5f
-
-55:
-       ; Error if H/w and S/w ASID don't match, but NOT if in kernel mode
-       lr  r2, [erstatus]
-       bbit0 r2, STATUS_U_BIT, 5f
-
-       ; We sure are in troubled waters, Flag the error, but to do so
-       ; need to switch to kernel mode stack to call error routine
-       GET_TSK_STACK_BASE   r3, sp
-
-       ; Call printk to shoutout aloud
-       mov r2, 1
-       j print_asid_mismatch
-
-5:     ; ASIDs match so proceed normally
-       nop
-
-#endif
-
-.endm
-
 ;============================================================================
 ;TLB Miss handling Code
 ;============================================================================