ARC: mm: move MMU specific bits out of entry code ...

[linux-2.6-microblaze.git] / arch / arc / include / asm / mmu.h

diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h
index 26b731d..e66e1e4 100644 (file)
--- a/arch/arc/include/asm/mmu.h
+++ b/arch/arc/include/asm/mmu.h
@@ -10,19 +10,10 @@
 #include <linux/threads.h>     /* NR_CPUS */
 #endif
 
-#if defined(CONFIG_ARC_MMU_V1)
-#define CONFIG_ARC_MMU_VER 1
-#elif defined(CONFIG_ARC_MMU_V2)
-#define CONFIG_ARC_MMU_VER 2
-#elif defined(CONFIG_ARC_MMU_V3)
-#define CONFIG_ARC_MMU_VER 3
-#elif defined(CONFIG_ARC_MMU_V4)
-#define CONFIG_ARC_MMU_VER 4
-#endif
-
 /* MMU Management regs */
 #define ARC_REG_MMU_BCR                0x06f
-#if (CONFIG_ARC_MMU_VER < 4)
+
+#ifdef CONFIG_ARC_MMU_V3
 #define ARC_REG_TLBPD0         0x405
 #define ARC_REG_TLBPD1         0x406
 #define ARC_REG_TLBPD1HI       0       /* Dummy: allows code sharing with ARC700 */
@@ -40,10 +31,6 @@
 #define ARC_REG_SCRATCH_DATA0  0x46c
 #endif
 
-#if defined(CONFIG_ISA_ARCV2) || !defined(CONFIG_SMP)
-#define        ARC_USE_SCRATCH_REG
-#endif
-
 /* Bits in MMU PID register */
 #define __TLB_ENABLE           (1 << 31)
 #define __PROG_ENABLE          (1 << 30)
@@ -52,7 +39,7 @@
 /* Error code if probe fails */
 #define TLB_LKUP_ERR           0x80000000
 
-#if (CONFIG_ARC_MMU_VER < 4)
+#ifdef CONFIG_ARC_MMU_V3
 #define TLB_DUP_ERR    (TLB_LKUP_ERR | 0x00000001)
 #else
 #define TLB_DUP_ERR    (TLB_LKUP_ERR | 0x40000000)
@@ -63,15 +50,10 @@
 #define TLBRead     0x2
 #define TLBGetIndex 0x3
 #define TLBProbe    0x4
-
-#if (CONFIG_ARC_MMU_VER >= 2)
 #define TLBWriteNI  0x5                /* write JTLB without inv uTLBs */
 #define TLBIVUTLB   0x6                /* explicitly inv uTLBs */
-#else
-#define TLBWriteNI  TLBWrite   /* Not present in hardware, fallback */
-#endif
 
-#if (CONFIG_ARC_MMU_VER >= 4)
+#ifdef CONFIG_ARC_MMU_V4
 #define TLBInsertEntry 0x7
 #define TLBDeleteEntry 0x8
 #endif
@@ -82,15 +64,18 @@ typedef struct {
        unsigned long asid[NR_CPUS];    /* 8 bit MMU PID + Generation cycle */
 } mm_context_t;
 
-#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
-void tlb_paranoid_check(unsigned int mm_asid, unsigned long address);
-#else
-#define tlb_paranoid_check(a, b)
-#endif
+static inline void mmu_setup_asid(struct mm_struct *mm, unsigned int asid)
+{
+       write_aux_reg(ARC_REG_PID, asid | MMU_ENABLE);
+}
 
-void arc_mmu_init(void);
-extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
-void read_decode_mmu_bcr(void);
+static inline void mmu_setup_pgd(struct mm_struct *mm, void *pgd)
+{
+       /* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */
+#ifdef CONFIG_ISA_ARCV2
+       write_aux_reg(ARC_REG_SCRATCH_DATA0, (unsigned int)pgd);
+#endif
+}
 
 static inline int is_pae40_enabled(void)
 {
@@ -99,6 +84,14 @@ static inline int is_pae40_enabled(void)
 
 extern int pae40_exist_but_not_enab(void);
 
+#else
+
+.macro ARC_MMU_REENABLE reg
+       lr \reg, [ARC_REG_PID]
+       or \reg, \reg, MMU_ENABLE
+       sr \reg, [ARC_REG_PID]
+.endm
+
 #endif /* !__ASSEMBLY__ */
 
 #endif