ARC: mm: vmalloc sync from kernel to user table to update PMD ...

[linux-2.6-microblaze.git] / arch / arc / Kconfig

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index d8f51eb..f631a7a 100644 (file)
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -116,16 +116,9 @@ choice
        default ARC_CPU_770 if ISA_ARCOMPACT
        default ARC_CPU_HS if ISA_ARCV2
 
-if ISA_ARCOMPACT
-
-config ARC_CPU_750D
-       bool "ARC750D"
-       select ARC_CANT_LLSC
-       help
-         Support for ARC750 core
-
 config ARC_CPU_770
        bool "ARC770"
+       depends on ISA_ARCOMPACT
        select ARC_HAS_SWAPE
        help
          Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
@@ -135,8 +128,6 @@ config ARC_CPU_770
          -Caches: New Prog Model, Region Flush
          -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
 
-endif #ISA_ARCOMPACT
-
 config ARC_CPU_HS
        bool "ARC-HS"
        depends on ISA_ARCV2
@@ -274,33 +265,17 @@ config ARC_DCCM_BASE
 
 choice
        prompt "MMU Version"
-       default ARC_MMU_V3 if ARC_CPU_770
-       default ARC_MMU_V2 if ARC_CPU_750D
-       default ARC_MMU_V4 if ARC_CPU_HS
-
-if ISA_ARCOMPACT
-
-config ARC_MMU_V1
-       bool "MMU v1"
-       help
-         Orig ARC700 MMU
-
-config ARC_MMU_V2
-       bool "MMU v2"
-       help
-         Fixed the deficiency of v1 - possible thrashing in memcpy scenario
-         when 2 D-TLB and 1 I-TLB entries index into same 2way set.
+       default ARC_MMU_V3 if ISA_ARCOMPACT
+       default ARC_MMU_V4 if ISA_ARCV2
 
 config ARC_MMU_V3
        bool "MMU v3"
-       depends on ARC_CPU_770
+       depends on ISA_ARCOMPACT
        help
          Introduced with ARC700 4.10: New Features
          Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
          Shared Address Spaces (SASID)
 
-endif
-
 config ARC_MMU_V4
        bool "MMU v4"
        depends on ISA_ARCV2
@@ -319,7 +294,6 @@ config ARC_PAGE_SIZE_8K
 
 config ARC_PAGE_SIZE_16K
        bool "16KB"
-       depends on ARC_MMU_V3 || ARC_MMU_V4
 
 config ARC_PAGE_SIZE_4K
        bool "4KB"
@@ -340,6 +314,10 @@ config ARC_HUGEPAGE_16M
 
 endchoice
 
+config PGTABLE_LEVELS
+       int "Number of Page table levels"
+       default 2
+
 config ARC_COMPACT_IRQ_LEVELS
        depends on ISA_ARCOMPACT
        bool "Setup Timer IRQ as high Priority"
@@ -409,7 +387,7 @@ choice
        help
          Depending on the configuration, CPU can contain DSP registers
          (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
-         Bellow is options describing how to handle these registers in
+         Below are options describing how to handle these registers in
          interrupt entry / exit and in context switch.
 
 config ARC_DSP_NONE
@@ -563,9 +541,6 @@ config ARC_DW2_UNWIND
          If you don't debug the kernel, you can say N, but we may not be able
          to solve problems without frame unwind information
 
-config ARC_DBG_TLB_PARANOIA
-       bool "Paranoia Checks in Low Level TLB Handlers"
-
 config ARC_DBG_JUMP_LABEL
        bool "Paranoid checks in Static Keys (jump labels) code"
        depends on JUMP_LABEL