Merge tag 'docs-5.11-2' of git://git.lwn.net/linux
[linux-2.6-microblaze.git] / Documentation / devicetree / bindings / memory-controllers / nvidia,tegra20-emc.txt
index 567cffd..cc443fc 100644 (file)
@@ -12,18 +12,44 @@ Properties:
   irrespective of ram-code configuration.
 - interrupts : Should contain EMC General interrupt.
 - clocks : Should contain EMC clock.
+- nvidia,memory-controller : Phandle of the Memory Controller node.
+- #interconnect-cells : Should be 0.
+- operating-points-v2: See ../bindings/opp/opp.txt for details.
+
+For each opp entry in 'operating-points-v2' table:
+- opp-supported-hw: One bitfield indicating SoC process ID mask
+
+       A bitwise AND is performed against this value and if any bit
+       matches, the OPP gets enabled.
+
+Optional properties:
+- core-supply: Phandle of voltage regulator of the SoC "core" power domain.
 
 Child device nodes describe the memory settings for different configurations and clock rates.
 
 Example:
 
+       opp_table: opp-table {
+               compatible = "operating-points-v2";
+
+               opp@36000000 {
+                       opp-microvolt = <950000 950000 1300000>;
+                       opp-hz = /bits/ 64 <36000000>;
+               };
+               ...
+       };
+
        memory-controller@7000f400 {
                #address-cells = < 1 >;
                #size-cells = < 0 >;
+               #interconnect-cells = <0>;
                compatible = "nvidia,tegra20-emc";
                reg = <0x7000f400 0x400>;
                interrupts = <0 78 0x04>;
                clocks = <&tegra_car TEGRA20_CLK_EMC>;
+               nvidia,memory-controller = <&mc>;
+               core-supply = <&core_vdd_reg>;
+               operating-points-v2 = <&opp_table>;
        }