Merge tag 'v5.9-rc2' into drm-misc-fixes

[linux-2.6-microblaze.git] / Documentation / devicetree / bindings / clock / qcom,gpucc.yaml

diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
index 679e7fe..df943c4 100644 (file)
--- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
@@ -10,31 +10,34 @@ maintainers:
   - Taniya Das <tdas@codeaurora.org>
 
 description: |
-  Qualcomm grpahics clock control module which supports the clocks, resets and
-  power domains.
+  Qualcomm graphics clock control module which supports the clocks, resets and
+  power domains on SDM845/SC7180/SM8150/SM8250.
+
+  See also:
+    dt-bindings/clock/qcom,gpucc-sdm845.h
+    dt-bindings/clock/qcom,gpucc-sc7180.h
+    dt-bindings/clock/qcom,gpucc-sm8150.h
+    dt-bindings/clock/qcom,gpucc-sm8250.h
 
 properties:
   compatible:
     enum:
-      - qcom,msm8998-gpucc
-      - qcom,sc7180-gpucc
       - qcom,sdm845-gpucc
+      - qcom,sc7180-gpucc
+      - qcom,sm8150-gpucc
+      - qcom,sm8250-gpucc
 
   clocks:
-    minItems: 1
-    maxItems: 3
     items:
       - description: Board XO source
-      - description: GPLL0 main branch source from GCC(gcc_gpu_gpll0_clk_src)
-      - description: GPLL0 div branch source from GCC(gcc_gpu_gpll0_div_clk_src)
+      - description: GPLL0 main branch source
+      - description: GPLL0 div branch source
 
   clock-names:
-    minItems: 1
-    maxItems: 3
     items:
-      - const: xo
-      - const: gpll0_main
-      - const: gpll0_div
+      - const: bi_tcxo
+      - const: gcc_gpu_gpll0_clk_src
+      - const: gcc_gpu_gpll0_div_clk_src
 
   '#clock-cells':
     const: 1
@@ -57,16 +60,23 @@ required:
   - '#reset-cells'
   - '#power-domain-cells'
 
+additionalProperties: false
+
 examples:
-  # Example of GPUCC with clock node properties for SDM845:
   - |
+    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
     clock-controller@5090000 {
       compatible = "qcom,sdm845-gpucc";
-      reg = <0x5090000 0x9000>;
-      clocks = <&rpmhcc 0>, <&gcc 31>, <&gcc 32>;
-      clock-names = "xo", "gpll0_main", "gpll0_div";
+      reg = <0x05090000 0x9000>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+      clock-names = "bi_tcxo",
+                    "gcc_gpu_gpll0_clk_src",
+                    "gcc_gpu_gpll0_div_clk_src";
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;
-     };
+    };
 ...