// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
 */

/dts-v1/;
#include "sparx5_pcb_common.dtsi"

/{
	aliases {
	    i2c0   = &i2c0;
	    i2c152 = &i2c152;
	    i2c153 = &i2c153;
	    i2c154 = &i2c154;
	    i2c155 = &i2c155;
	};

	gpio-restart {
		compatible = "gpio-restart";
		gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
		priority = <200>;
	};

	leds {
		compatible = "gpio-leds";
		led@0 {
			label = "eth60:yellow";
			gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
		led@1 {
			label = "eth60:green";
			gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
		led@2 {
			label = "eth61:yellow";
			gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
		led@3 {
			label = "eth61:green";
			gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
		led@4 {
			label = "eth62:yellow";
			gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
		led@5 {
			label = "eth62:green";
			gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
		led@6 {
			label = "eth63:yellow";
			gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
		led@7 {
			label = "eth63:green";
			gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
	};
};

&gpio {
	i2cmux_pins_i: i2cmux-pins-i {
	       pins = "GPIO_35", "GPIO_36",
		      "GPIO_50", "GPIO_51";
		function = "twi_scl_m";
		output-low;
	};
	i2cmux_s29: i2cmux-0 {
		pins = "GPIO_35";
		function = "twi_scl_m";
		output-high;
	};
	i2cmux_s30: i2cmux-1 {
		pins = "GPIO_36";
		function = "twi_scl_m";
		output-high;
	};
	i2cmux_s31: i2cmux-2 {
		pins = "GPIO_50";
		function = "twi_scl_m";
		output-high;
	};
	i2cmux_s32: i2cmux-3 {
		pins = "GPIO_51";
		function = "twi_scl_m";
		output-high;
	};
};

&spi0 {
	status = "okay";
	spi@0 {
		compatible = "spi-mux";
		mux-controls = <&mux>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0>; /* CS0 */
		spi-flash@9 {
			compatible = "jedec,spi-nor";
			spi-max-frequency = <8000000>;
			reg = <0x9>; /* SPI */
		};
	};
};

&spi0 {
	status = "okay";
	spi@0 {
		compatible = "spi-mux";
		mux-controls = <&mux>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0>; /* CS0 */
		spi-flash@9 {
			compatible = "jedec,spi-nor";
			spi-max-frequency = <8000000>;
			reg = <0x9>; /* SPI */
		};
	};
};

&sgpio1 {
	status = "okay";
	microchip,sgpio-port-ranges = <24 31>;
	gpio@0 {
		ngpios = <64>;
	};
	gpio@1 {
		ngpios = <64>;
	};
};

&axi {
	i2c0_imux: i2c0-imux@0 {
		compatible = "i2c-mux-pinctrl";
		#address-cells = <1>;
		#size-cells = <0>;
		i2c-parent = <&i2c0>;
	};
};

&i2c0_imux {
	pinctrl-names =
		"i2c152", "i2c153", "i2c154", "i2c155",
		"idle";
	pinctrl-0 = <&i2cmux_s29>;
	pinctrl-1 = <&i2cmux_s30>;
	pinctrl-2 = <&i2cmux_s31>;
	pinctrl-3 = <&i2cmux_s32>;
	pinctrl-4 = <&i2cmux_pins_i>;
	i2c152: i2c_sfp1 {
		reg = <0x0>;
		#address-cells = <1>;
		#size-cells = <0>;
	};
	i2c153: i2c_sfp2 {
		reg = <0x1>;
		#address-cells = <1>;
		#size-cells = <0>;
	};
	i2c154: i2c_sfp3 {
		reg = <0x2>;
		#address-cells = <1>;
		#size-cells = <0>;
	};
	i2c155: i2c_sfp4 {
		reg = <0x3>;
		#address-cells = <1>;
		#size-cells = <0>;
	};
};