tools/perf/pmu-events/arch/x86/icelakex/floating-point.json

   1 [
   2     {
   3         "BriefDescription": "Counts all microcode FP assists.",
   4         "CollectPEBSRecord": "2",
   5         "Counter": "0,1,2,3,4,5,6,7",
   6         "EventCode": "0xc1",
   7         "EventName": "ASSISTS.FP",
   8         "PEBScounters": "0,1,2,3,4,5,6,7",
   9         "PublicDescription": "Counts all microcode Floating Point assists.",
  10         "SampleAfterValue": "100003",
  11         "Speculative": "1",
  12         "UMask": "0x2"
  13     },
  14     {
  15         "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
  16         "CollectPEBSRecord": "2",
  17         "Counter": "0,1,2,3,4,5,6,7",
  18         "EventCode": "0xc7",
  19         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
  20         "PEBScounters": "0,1,2,3,4,5,6,7",
  21         "SampleAfterValue": "100003",
  22         "UMask": "0x1"
  23     },
  24     {
  25         "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
  26         "CollectPEBSRecord": "2",
  27         "Counter": "0,1,2,3,4,5,6,7",
  28         "EventCode": "0xc7",
  29         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
  30         "PEBScounters": "0,1,2,3,4,5,6,7",
  31         "SampleAfterValue": "100003",
  32         "UMask": "0x2"
  33     },
  34     {
  35         "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
  36         "CollectPEBSRecord": "2",
  37         "Counter": "0,1,2,3,4,5,6,7",
  38         "EventCode": "0xc7",
  39         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
  40         "PEBScounters": "0,1,2,3,4,5,6,7",
  41         "SampleAfterValue": "100003",
  42         "UMask": "0x4"
  43     },
  44     {
  45         "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
  46         "CollectPEBSRecord": "2",
  47         "Counter": "0,1,2,3,4,5,6,7",
  48         "EventCode": "0xc7",
  49         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
  50         "PEBScounters": "0,1,2,3,4,5,6,7",
  51         "PublicDescription": "Counts number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
  52         "SampleAfterValue": "100003",
  53         "UMask": "0x8"
  54     },
  55     {
  56         "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
  57         "CollectPEBSRecord": "2",
  58         "Counter": "0,1,2,3,4,5,6,7",
  59         "EventCode": "0xc7",
  60         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
  61         "PEBScounters": "0,1,2,3,4,5,6,7",
  62         "SampleAfterValue": "100003",
  63         "UMask": "0x10"
  64     },
  65     {
  66         "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
  67         "CollectPEBSRecord": "2",
  68         "Counter": "0,1,2,3,4,5,6,7",
  69         "EventCode": "0xc7",
  70         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
  71         "PEBScounters": "0,1,2,3,4,5,6,7",
  72         "SampleAfterValue": "100003",
  73         "UMask": "0x20"
  74     },
  75     {
  76         "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
  77         "CollectPEBSRecord": "2",
  78         "Counter": "0,1,2,3,4,5,6,7",
  79         "EventCode": "0xc7",
  80         "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
  81         "PEBScounters": "0,1,2,3,4,5,6,7",
  82         "SampleAfterValue": "100003",
  83         "UMask": "0x40"
  84     },
  85     {
  86         "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
  87         "CollectPEBSRecord": "2",
  88         "Counter": "0,1,2,3,4,5,6,7",
  89         "EventCode": "0xc7",
  90         "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
  91         "PEBScounters": "0,1,2,3,4,5,6,7",
  92         "SampleAfterValue": "100003",
  93         "UMask": "0x80"
  94     }
  95 ]