3 "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
4 "CollectPEBSRecord": "2",
7 "EventName": "TX_MEM.ABORT_CONFLICT",
8 "PEBScounters": "0,1,2,3",
9 "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
10 "SampleAfterValue": "100003",
15 "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
16 "CollectPEBSRecord": "2",
17 "Counter": "0,1,2,3,4,5,6,7",
19 "EventName": "HLE_RETIRED.ABORTED",
20 "PEBScounters": "0,1,2,3,4,5,6,7",
21 "PublicDescription": "Counts the number of times HLE abort was triggered.",
22 "SampleAfterValue": "100003",
26 "BriefDescription": "Counts demand data reads that was not supplied by the L3 cache.",
27 "CollectPEBSRecord": "2",
29 "EventCode": "0xB7, 0xBB",
30 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
31 "MSRIndex": "0x1a6,0x1a7",
32 "MSRValue": "0x3FFFC00001",
34 "PEBScounters": "0,1,2,3",
35 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
36 "SampleAfterValue": "100003",
41 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
42 "CollectPEBSRecord": "2",
43 "Counter": "0,1,2,3,4,5,6,7",
46 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
50 "PEBScounters": "0,1,2,3,4,5,6,7",
51 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
52 "SampleAfterValue": "20011",
57 "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that was not supplied by the L3 cache.",
58 "CollectPEBSRecord": "2",
60 "EventCode": "0xB7, 0xBB",
61 "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS",
62 "MSRIndex": "0x1a6,0x1a7",
63 "MSRValue": "0x3FFFC00010",
65 "PEBScounters": "0,1,2,3",
66 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
67 "SampleAfterValue": "100003",
72 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
73 "CollectPEBSRecord": "2",
74 "Counter": "0,1,2,3,4,5,6,7",
76 "EventName": "HLE_RETIRED.ABORTED_MEM",
77 "PEBScounters": "0,1,2,3,4,5,6,7",
78 "PublicDescription": "Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
79 "SampleAfterValue": "100003",
83 "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
84 "CollectPEBSRecord": "2",
87 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
88 "PEBScounters": "0,1,2,3",
89 "PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
90 "SampleAfterValue": "100003",
95 "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
96 "CollectPEBSRecord": "2",
99 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
100 "PEBScounters": "0,1,2,3",
101 "PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
102 "SampleAfterValue": "100003",
107 "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded",
108 "CollectPEBSRecord": "2",
109 "Counter": "0,1,2,3,4,5,6,7",
111 "EventName": "TX_EXEC.MISC3",
112 "PEBScounters": "0,1,2,3,4,5,6,7",
113 "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
114 "SampleAfterValue": "100003",
119 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
120 "CollectPEBSRecord": "2",
121 "Counter": "0,1,2,3,4,5,6,7",
123 "EventName": "TX_EXEC.MISC2",
124 "PEBScounters": "0,1,2,3,4,5,6,7",
125 "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
126 "SampleAfterValue": "100003",
131 "BriefDescription": "Cycles where data return is pending for a Demand Data Read request who miss L3 cache.",
132 "CollectPEBSRecord": "2",
133 "Counter": "0,1,2,3",
136 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
137 "PEBScounters": "0,1,2,3",
138 "PublicDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
139 "SampleAfterValue": "1000003",
144 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.",
145 "CollectPEBSRecord": "2",
146 "Counter": "0,1,2,3",
147 "EventCode": "0xB7, 0xBB",
148 "EventName": "OCR.DEMAND_RFO.L3_MISS",
149 "MSRIndex": "0x1a6,0x1a7",
150 "MSRValue": "0x3FFFC00002",
152 "PEBScounters": "0,1,2,3",
153 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
154 "SampleAfterValue": "100003",
159 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
160 "CollectPEBSRecord": "2",
161 "Counter": "0,1,2,3,4,5,6,7",
164 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
168 "PEBScounters": "0,1,2,3,4,5,6,7",
169 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
170 "SampleAfterValue": "101",
175 "BriefDescription": "Number of times an RTM execution successfully committed",
176 "CollectPEBSRecord": "2",
177 "Counter": "0,1,2,3,4,5,6,7",
179 "EventName": "RTM_RETIRED.COMMIT",
180 "PEBScounters": "0,1,2,3,4,5,6,7",
181 "PublicDescription": "Counts the number of times RTM commit succeeded.",
182 "SampleAfterValue": "100003",
186 "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
187 "CollectPEBSRecord": "2",
188 "Counter": "0,1,2,3",
190 "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
191 "PEBScounters": "0,1,2,3",
192 "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
193 "SampleAfterValue": "100003",
198 "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
199 "CollectPEBSRecord": "2",
200 "Counter": "0,1,2,3,4,5,6,7",
202 "EventName": "HLE_RETIRED.ABORTED_EVENTS",
203 "PEBScounters": "0,1,2,3,4,5,6,7",
204 "PublicDescription": "Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
205 "SampleAfterValue": "100003",
209 "BriefDescription": "Number of times an HLE execution successfully committed",
210 "CollectPEBSRecord": "2",
211 "Counter": "0,1,2,3,4,5,6,7",
213 "EventName": "HLE_RETIRED.COMMIT",
214 "PEBScounters": "0,1,2,3,4,5,6,7",
215 "PublicDescription": "Counts the number of times HLE commit succeeded.",
216 "SampleAfterValue": "100003",
220 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
221 "CollectPEBSRecord": "2",
222 "Counter": "0,1,2,3,4,5,6,7",
224 "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
225 "PEBScounters": "0,1,2,3,4,5,6,7",
226 "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
227 "SampleAfterValue": "100003",
231 "BriefDescription": "Number of machine clears due to memory ordering conflicts.",
232 "CollectPEBSRecord": "2",
233 "Counter": "0,1,2,3,4,5,6,7",
235 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
236 "PEBScounters": "0,1,2,3,4,5,6,7",
237 "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
238 "SampleAfterValue": "100003",
243 "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
244 "CollectPEBSRecord": "2",
245 "Counter": "0,1,2,3",
247 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
248 "PEBScounters": "0,1,2,3",
249 "PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
250 "SampleAfterValue": "100003",
255 "BriefDescription": "Counts streaming stores that was not supplied by the L3 cache.",
256 "CollectPEBSRecord": "2",
257 "Counter": "0,1,2,3",
258 "EventCode": "0xB7, 0xBB",
259 "EventName": "OCR.STREAMING_WR.L3_MISS",
260 "MSRIndex": "0x1a6,0x1a7",
261 "MSRValue": "0x3FFFC00800",
263 "PEBScounters": "0,1,2,3",
264 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
265 "SampleAfterValue": "100003",
270 "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
271 "CollectPEBSRecord": "2",
272 "Counter": "0,1,2,3",
274 "EventName": "TX_MEM.ABORT_CAPACITY_READ",
275 "PEBScounters": "0,1,2,3",
276 "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
277 "SampleAfterValue": "100003",
282 "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cache.",
283 "CollectPEBSRecord": "2",
284 "Counter": "0,1,2,3",
285 "EventCode": "0xB7, 0xBB",
286 "EventName": "OCR.OTHER.L3_MISS",
287 "MSRIndex": "0x1a6,0x1a7",
288 "MSRValue": "0x3FFFC08000",
290 "PEBScounters": "0,1,2,3",
291 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
292 "SampleAfterValue": "100003",
297 "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that was not supplied by the L3 cache.",
298 "CollectPEBSRecord": "2",
299 "Counter": "0,1,2,3",
300 "EventCode": "0xB7, 0xBB",
301 "EventName": "OCR.HWPF_L2_RFO.L3_MISS",
302 "MSRIndex": "0x1a6,0x1a7",
303 "MSRValue": "0x3FFFC00020",
305 "PEBScounters": "0,1,2,3",
306 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
307 "SampleAfterValue": "100003",
312 "BriefDescription": "Demand Data Read requests who miss L3 cache",
313 "CollectPEBSRecord": "2",
314 "Counter": "0,1,2,3",
316 "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
317 "PEBScounters": "0,1,2,3",
318 "PublicDescription": "Demand Data Read requests who miss L3 cache.",
319 "SampleAfterValue": "100003",
324 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
325 "CollectPEBSRecord": "2",
326 "Counter": "0,1,2,3",
329 "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
330 "PEBScounters": "0,1,2,3",
331 "SampleAfterValue": "1000003",
336 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
337 "CollectPEBSRecord": "2",
338 "Counter": "0,1,2,3,4,5,6,7",
340 "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
341 "PEBScounters": "0,1,2,3,4,5,6,7",
342 "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
343 "SampleAfterValue": "100003",
347 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
348 "CollectPEBSRecord": "2",
349 "Counter": "0,1,2,3,4,5,6,7",
351 "EventName": "RTM_RETIRED.ABORTED_EVENTS",
352 "PEBScounters": "0,1,2,3,4,5,6,7",
353 "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
354 "SampleAfterValue": "100003",
358 "BriefDescription": "Number of times an HLE execution started.",
359 "CollectPEBSRecord": "2",
360 "Counter": "0,1,2,3,4,5,6,7",
362 "EventName": "HLE_RETIRED.START",
363 "PEBScounters": "0,1,2,3,4,5,6,7",
364 "PublicDescription": "Counts the number of times we entered an HLE region. Does not count nested transactions.",
365 "SampleAfterValue": "100003",
369 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
370 "CollectPEBSRecord": "2",
371 "Counter": "0,1,2,3,4,5,6,7",
374 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
378 "PEBScounters": "0,1,2,3,4,5,6,7",
379 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
380 "SampleAfterValue": "100003",
385 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
386 "CollectPEBSRecord": "2",
387 "Counter": "0,1,2,3,4,5,6,7",
390 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
394 "PEBScounters": "0,1,2,3,4,5,6,7",
395 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
396 "SampleAfterValue": "1009",
401 "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
402 "CollectPEBSRecord": "2",
403 "Counter": "0,1,2,3",
405 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
406 "PEBScounters": "0,1,2,3",
407 "PublicDescription": "Counts the number of times we could not allocate Lock Buffer.",
408 "SampleAfterValue": "100003",
413 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
414 "CollectPEBSRecord": "2",
415 "Counter": "0,1,2,3,4,5,6,7",
418 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
422 "PEBScounters": "0,1,2,3,4,5,6,7",
423 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
424 "SampleAfterValue": "50021",
429 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
430 "CollectPEBSRecord": "2",
431 "Counter": "0,1,2,3,4,5,6,7",
434 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
438 "PEBScounters": "0,1,2,3,4,5,6,7",
439 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
440 "SampleAfterValue": "503",
445 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
446 "CollectPEBSRecord": "2",
447 "Counter": "0,1,2,3",
450 "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
451 "PEBScounters": "0,1,2,3",
452 "SampleAfterValue": "1000003",
457 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
458 "CollectPEBSRecord": "2",
459 "Counter": "0,1,2,3,4,5,6,7",
462 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
466 "PEBScounters": "0,1,2,3,4,5,6,7",
467 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
468 "SampleAfterValue": "2003",
473 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
474 "CollectPEBSRecord": "2",
475 "Counter": "0,1,2,3,4,5,6,7",
478 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
482 "PEBScounters": "0,1,2,3,4,5,6,7",
483 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
484 "SampleAfterValue": "100007",
489 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
490 "CollectPEBSRecord": "2",
491 "Counter": "0,1,2,3,4,5,6,7",
493 "EventName": "RTM_RETIRED.ABORTED_MEM",
494 "PEBScounters": "0,1,2,3,4,5,6,7",
495 "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
496 "SampleAfterValue": "100003",
500 "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache.",
501 "CollectPEBSRecord": "2",
502 "Counter": "0,1,2,3",
503 "EventCode": "0xB7, 0xBB",
504 "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS",
505 "MSRIndex": "0x1a6,0x1a7",
506 "MSRValue": "0x3FFFC00400",
508 "PEBScounters": "0,1,2,3",
509 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
510 "SampleAfterValue": "100003",
515 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache.",
516 "CollectPEBSRecord": "2",
517 "Counter": "0,1,2,3",
518 "EventCode": "0xB7, 0xBB",
519 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
520 "MSRIndex": "0x1a6,0x1a7",
521 "MSRValue": "0x3FFFC00004",
523 "PEBScounters": "0,1,2,3",
524 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
525 "SampleAfterValue": "100003",
530 "BriefDescription": "Number of times an RTM execution aborted.",
531 "CollectPEBSRecord": "2",
532 "Counter": "0,1,2,3,4,5,6,7",
534 "EventName": "RTM_RETIRED.ABORTED",
535 "PEBScounters": "0,1,2,3,4,5,6,7",
536 "PublicDescription": "Counts the number of times RTM abort was triggered.",
537 "SampleAfterValue": "100003",
541 "BriefDescription": "Number of times an RTM execution started.",
542 "CollectPEBSRecord": "2",
543 "Counter": "0,1,2,3,4,5,6,7",
545 "EventName": "RTM_RETIRED.START",
546 "PEBScounters": "0,1,2,3,4,5,6,7",
547 "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
548 "SampleAfterValue": "100003",
552 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
553 "CollectPEBSRecord": "2",
554 "Counter": "0,1,2,3,4,5,6,7",
556 "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
557 "PEBScounters": "0,1,2,3,4,5,6,7",
558 "PublicDescription": "Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
559 "SampleAfterValue": "100003",
563 "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
564 "CollectPEBSRecord": "2",
565 "Counter": "0,1,2,3",
567 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
568 "PEBScounters": "0,1,2,3",
569 "PublicDescription": "Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
570 "SampleAfterValue": "100003",