sound/pci/hda/hda_intel.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  hda_intel.c - Implementation of primary alsa driver code base
   5  *                for Intel HD Audio.
   6  *
   7  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   8  *
   9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  10  *                     PeiSen Hou <pshou@realtek.com.tw>
  11  *
  12  *  CONTACTS:
  13  *
  14  *  Matt Jared          matt.jared@intel.com
  15  *  Andy Kopp           andy.kopp@intel.com
  16  *  Dan Kogan           dan.d.kogan@intel.com
  17  *
  18  *  CHANGES:
  19  *
  20  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/mutex.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/time.h>
  37 #include <linux/completion.h>
  38 #include <linux/acpi.h>
  39 #include <linux/pgtable.h>
  40
  41 #ifdef CONFIG_X86
  42 /* for snoop control */
  43 #include <asm/set_memory.h>
  44 #include <asm/cpufeature.h>
  45 #endif
  46 #include <sound/core.h>
  47 #include <sound/initval.h>
  48 #include <sound/hdaudio.h>
  49 #include <sound/hda_i915.h>
  50 #include <sound/intel-dsp-config.h>
  51 #include <linux/vgaarb.h>
  52 #include <linux/vga_switcheroo.h>
  53 #include <linux/firmware.h>
  54 #include <sound/hda_codec.h>
  55 #include "hda_controller.h"
  56 #include "hda_intel.h"
  57
  58 #define CREATE_TRACE_POINTS
  59 #include "hda_intel_trace.h"
  60
  61 /* position fix mode */
  62 enum {
  63         POS_FIX_AUTO,
  64         POS_FIX_LPIB,
  65         POS_FIX_POSBUF,
  66         POS_FIX_VIACOMBO,
  67         POS_FIX_COMBO,
  68         POS_FIX_SKL,
  69         POS_FIX_FIFO,
  70 };
  71
  72 /* Defines for ATI HD Audio support in SB450 south bridge */
  73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  75
  76 /* Defines for Nvidia HDA support */
  77 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  78 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  79 #define NVIDIA_HDA_ISTRM_COH          0x4d
  80 #define NVIDIA_HDA_OSTRM_COH          0x4c
  81 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  82
  83 /* Defines for Intel SCH HDA snoop control */
  84 #define INTEL_HDA_CGCTL  0x48
  85 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  86 #define INTEL_SCH_HDA_DEVC      0x78
  87 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  88
  89 /* Define VIA HD Audio Device ID*/
  90 #define VIA_HDAC_DEVICE_ID              0x3288
  91
  92 /* max number of SDs */
  93 /* ICH, ATI and VIA have 4 playback and 4 capture */
  94 #define ICH6_NUM_CAPTURE        4
  95 #define ICH6_NUM_PLAYBACK       4
  96
  97 /* ULI has 6 playback and 5 capture */
  98 #define ULI_NUM_CAPTURE         5
  99 #define ULI_NUM_PLAYBACK        6
 100
 101 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 102 #define ATIHDMI_NUM_CAPTURE     0
 103 #define ATIHDMI_NUM_PLAYBACK    8
 104
 105 /* TERA has 4 playback and 3 capture */
 106 #define TERA_NUM_CAPTURE        3
 107 #define TERA_NUM_PLAYBACK       4
 108
 109
 110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 113 static char *model[SNDRV_CARDS];
 114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 117 static int probe_only[SNDRV_CARDS];
 118 static int jackpoll_ms[SNDRV_CARDS];
 119 static int single_cmd = -1;
 120 static int enable_msi = -1;
 121 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 122 static char *patch[SNDRV_CARDS];
 123 #endif
 124 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 126                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 127 #endif
 128 static bool dmic_detect = 1;
 129
 130 module_param_array(index, int, NULL, 0444);
 131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 132 module_param_array(id, charp, NULL, 0444);
 133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 134 module_param_array(enable, bool, NULL, 0444);
 135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 136 module_param_array(model, charp, NULL, 0444);
 137 MODULE_PARM_DESC(model, "Use the given board model.");
 138 module_param_array(position_fix, int, NULL, 0444);
 139 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 140                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
 141 module_param_array(bdl_pos_adj, int, NULL, 0644);
 142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 143 module_param_array(probe_mask, int, NULL, 0444);
 144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 145 module_param_array(probe_only, int, NULL, 0444);
 146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 147 module_param_array(jackpoll_ms, int, NULL, 0444);
 148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 149 module_param(single_cmd, bint, 0444);
 150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 151                  "(for debugging only).");
 152 module_param(enable_msi, bint, 0444);
 153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 154 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 155 module_param_array(patch, charp, NULL, 0444);
 156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 157 #endif
 158 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 159 module_param_array(beep_mode, bool, NULL, 0444);
 160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 161                             "(0=off, 1=on) (default=1).");
 162 #endif
 163 module_param(dmic_detect, bool, 0444);
 164 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
 165                              "(0=off, 1=on) (default=1); "
 166                  "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
 167
 168 #ifdef CONFIG_PM
 169 static int param_set_xint(const char *val, const struct kernel_param *kp);
 170 static const struct kernel_param_ops param_ops_xint = {
 171         .set = param_set_xint,
 172         .get = param_get_int,
 173 };
 174 #define param_check_xint param_check_int
 175
 176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 177 module_param(power_save, xint, 0644);
 178 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 179                  "(in second, 0 = disable).");
 180
 181 static bool pm_blacklist = true;
 182 module_param(pm_blacklist, bool, 0644);
 183 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
 184
 185 /* reset the HD-audio controller in power save mode.
 186  * this may give more power-saving, but will take longer time to
 187  * wake up.
 188  */
 189 static bool power_save_controller = 1;
 190 module_param(power_save_controller, bool, 0644);
 191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 192 #else
 193 #define power_save      0
 194 #endif /* CONFIG_PM */
 195
 196 static int align_buffer_size = -1;
 197 module_param(align_buffer_size, bint, 0644);
 198 MODULE_PARM_DESC(align_buffer_size,
 199                 "Force buffer and period sizes to be multiple of 128 bytes.");
 200
 201 #ifdef CONFIG_X86
 202 static int hda_snoop = -1;
 203 module_param_named(snoop, hda_snoop, bint, 0444);
 204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 205 #else
 206 #define hda_snoop               true
 207 #endif
 208
 209
 210 MODULE_LICENSE("GPL");
 211 MODULE_DESCRIPTION("Intel HDA driver");
 212
 213 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 214 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 215 #define SUPPORT_VGA_SWITCHEROO
 216 #endif
 217 #endif
 218
 219
 220 /*
 221  */
 222
 223 /* driver types */
 224 enum {
 225         AZX_DRIVER_ICH,
 226         AZX_DRIVER_PCH,
 227         AZX_DRIVER_SCH,
 228         AZX_DRIVER_SKL,
 229         AZX_DRIVER_HDMI,
 230         AZX_DRIVER_ATI,
 231         AZX_DRIVER_ATIHDMI,
 232         AZX_DRIVER_ATIHDMI_NS,
 233         AZX_DRIVER_VIA,
 234         AZX_DRIVER_SIS,
 235         AZX_DRIVER_ULI,
 236         AZX_DRIVER_NVIDIA,
 237         AZX_DRIVER_TERA,
 238         AZX_DRIVER_CTX,
 239         AZX_DRIVER_CTHDA,
 240         AZX_DRIVER_CMEDIA,
 241         AZX_DRIVER_ZHAOXIN,
 242         AZX_DRIVER_GENERIC,
 243         AZX_NUM_DRIVERS, /* keep this as last entry */
 244 };
 245
 246 #define azx_get_snoop_type(chip) \
 247         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 248 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 249
 250 /* quirks for old Intel chipsets */
 251 #define AZX_DCAPS_INTEL_ICH \
 252         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 253
 254 /* quirks for Intel PCH */
 255 #define AZX_DCAPS_INTEL_PCH_BASE \
 256         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 257          AZX_DCAPS_SNOOP_TYPE(SCH))
 258
 259 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 260 #define AZX_DCAPS_INTEL_PCH_NOPM \
 261         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 262
 263 /* PCH for HSW/BDW; with runtime PM */
 264 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 265 #define AZX_DCAPS_INTEL_PCH \
 266         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 267
 268 /* HSW HDMI */
 269 #define AZX_DCAPS_INTEL_HASWELL \
 270         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 271          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 272          AZX_DCAPS_SNOOP_TYPE(SCH))
 273
 274 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 275 #define AZX_DCAPS_INTEL_BROADWELL \
 276         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 277          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 278          AZX_DCAPS_SNOOP_TYPE(SCH))
 279
 280 #define AZX_DCAPS_INTEL_BAYTRAIL \
 281         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 282
 283 #define AZX_DCAPS_INTEL_BRASWELL \
 284         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 285          AZX_DCAPS_I915_COMPONENT)
 286
 287 #define AZX_DCAPS_INTEL_SKYLAKE \
 288         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 289          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 290
 291 #define AZX_DCAPS_INTEL_BROXTON         AZX_DCAPS_INTEL_SKYLAKE
 292
 293 /* quirks for ATI SB / AMD Hudson */
 294 #define AZX_DCAPS_PRESET_ATI_SB \
 295         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
 296          AZX_DCAPS_SNOOP_TYPE(ATI))
 297
 298 /* quirks for ATI/AMD HDMI */
 299 #define AZX_DCAPS_PRESET_ATI_HDMI \
 300         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
 301          AZX_DCAPS_NO_MSI64)
 302
 303 /* quirks for ATI HDMI with snoop off */
 304 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 305         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 306
 307 /* quirks for AMD SB */
 308 #define AZX_DCAPS_PRESET_AMD_SB \
 309         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
 310          AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
 311
 312 /* quirks for Nvidia */
 313 #define AZX_DCAPS_PRESET_NVIDIA \
 314         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 315          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 316
 317 #define AZX_DCAPS_PRESET_CTHDA \
 318         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 319          AZX_DCAPS_NO_64BIT |\
 320          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 321
 322 /*
 323  * vga_switcheroo support
 324  */
 325 #ifdef SUPPORT_VGA_SWITCHEROO
 326 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 327 #define needs_eld_notify_link(chip)     ((chip)->bus.keep_power)
 328 #else
 329 #define use_vga_switcheroo(chip)        0
 330 #define needs_eld_notify_link(chip)     false
 331 #endif
 332
 333 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 334                                         ((pci)->device == 0x0c0c) || \
 335                                         ((pci)->device == 0x0d0c) || \
 336                                         ((pci)->device == 0x160c) || \
 337                                         ((pci)->device == 0x490d))
 338
 339 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 340
 341 static const char * const driver_short_names[] = {
 342         [AZX_DRIVER_ICH] = "HDA Intel",
 343         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 344         [AZX_DRIVER_SCH] = "HDA Intel MID",
 345         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 346         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 347         [AZX_DRIVER_ATI] = "HDA ATI SB",
 348         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 349         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 350         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 351         [AZX_DRIVER_SIS] = "HDA SIS966",
 352         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 353         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 354         [AZX_DRIVER_TERA] = "HDA Teradici",
 355         [AZX_DRIVER_CTX] = "HDA Creative",
 356         [AZX_DRIVER_CTHDA] = "HDA Creative",
 357         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 358         [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
 359         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 360 };
 361
 362 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 363 static void set_default_power_save(struct azx *chip);
 364
 365 /*
 366  * initialize the PCI registers
 367  */
 368 /* update bits in a PCI register byte */
 369 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 370                             unsigned char mask, unsigned char val)
 371 {
 372         unsigned char data;
 373
 374         pci_read_config_byte(pci, reg, &data);
 375         data &= ~mask;
 376         data |= (val & mask);
 377         pci_write_config_byte(pci, reg, data);
 378 }
 379
 380 static void azx_init_pci(struct azx *chip)
 381 {
 382         int snoop_type = azx_get_snoop_type(chip);
 383
 384         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 385          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 386          * Ensuring these bits are 0 clears playback static on some HD Audio
 387          * codecs.
 388          * The PCI register TCSEL is defined in the Intel manuals.
 389          */
 390         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 391                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 392                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 393         }
 394
 395         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 396          * we need to enable snoop.
 397          */
 398         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 399                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 400                         azx_snoop(chip));
 401                 update_pci_byte(chip->pci,
 402                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 403                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 404         }
 405
 406         /* For NVIDIA HDA, enable snoop */
 407         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 408                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 409                         azx_snoop(chip));
 410                 update_pci_byte(chip->pci,
 411                                 NVIDIA_HDA_TRANSREG_ADDR,
 412                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 413                 update_pci_byte(chip->pci,
 414                                 NVIDIA_HDA_ISTRM_COH,
 415                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 416                 update_pci_byte(chip->pci,
 417                                 NVIDIA_HDA_OSTRM_COH,
 418                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 419         }
 420
 421         /* Enable SCH/PCH snoop if needed */
 422         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 423                 unsigned short snoop;
 424                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 425                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 426                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 427                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 428                         if (!azx_snoop(chip))
 429                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 430                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 431                         pci_read_config_word(chip->pci,
 432                                 INTEL_SCH_HDA_DEVC, &snoop);
 433                 }
 434                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 435                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 436                         "Disabled" : "Enabled");
 437         }
 438 }
 439
 440 /*
 441  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 442  * and makes an audio stream sensitive to system latencies when
 443  * 24/32 bits are playing.
 444  * Adjusting threshold of DMA fifo to force the DMA request
 445  * sooner to improve latency tolerance at the expense of power.
 446  */
 447 static void bxt_reduce_dma_latency(struct azx *chip)
 448 {
 449         u32 val;
 450
 451         val = azx_readl(chip, VS_EM4L);
 452         val &= (0x3 << 20);
 453         azx_writel(chip, VS_EM4L, val);
 454 }
 455
 456 /*
 457  * ML_LCAP bits:
 458  *  bit 0: 6 MHz Supported
 459  *  bit 1: 12 MHz Supported
 460  *  bit 2: 24 MHz Supported
 461  *  bit 3: 48 MHz Supported
 462  *  bit 4: 96 MHz Supported
 463  *  bit 5: 192 MHz Supported
 464  */
 465 static int intel_get_lctl_scf(struct azx *chip)
 466 {
 467         struct hdac_bus *bus = azx_bus(chip);
 468         static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
 469         u32 val, t;
 470         int i;
 471
 472         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 473
 474         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 475                 t = preferred_bits[i];
 476                 if (val & (1 << t))
 477                         return t;
 478         }
 479
 480         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 481         return 0;
 482 }
 483
 484 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 485 {
 486         struct hdac_bus *bus = azx_bus(chip);
 487         u32 val;
 488         int timeout;
 489
 490         /*
 491          * the codecs are sharing the first link setting by default
 492          * If other links are enabled for stream, they need similar fix
 493          */
 494         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 495         val &= ~AZX_MLCTL_SPA;
 496         val |= state << AZX_MLCTL_SPA_SHIFT;
 497         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 498         /* wait for CPA */
 499         timeout = 50;
 500         while (timeout) {
 501                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 502                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 503                         return 0;
 504                 timeout--;
 505                 udelay(10);
 506         }
 507
 508         return -1;
 509 }
 510
 511 static void intel_init_lctl(struct azx *chip)
 512 {
 513         struct hdac_bus *bus = azx_bus(chip);
 514         u32 val;
 515         int ret;
 516
 517         /* 0. check lctl register value is correct or not */
 518         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 519         /* if SCF is already set, let's use it */
 520         if ((val & ML_LCTL_SCF_MASK) != 0)
 521                 return;
 522
 523         /*
 524          * Before operating on SPA, CPA must match SPA.
 525          * Any deviation may result in undefined behavior.
 526          */
 527         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 528                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 529                 return;
 530
 531         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 532         ret = intel_ml_lctl_set_power(chip, 0);
 533         udelay(100);
 534         if (ret)
 535                 goto set_spa;
 536
 537         /* 2. update SCF to select a properly audio clock*/
 538         val &= ~ML_LCTL_SCF_MASK;
 539         val |= intel_get_lctl_scf(chip);
 540         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 541
 542 set_spa:
 543         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 544         intel_ml_lctl_set_power(chip, 1);
 545         udelay(100);
 546 }
 547
 548 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 549 {
 550         struct hdac_bus *bus = azx_bus(chip);
 551         struct pci_dev *pci = chip->pci;
 552         u32 val;
 553
 554         snd_hdac_set_codec_wakeup(bus, true);
 555         if (chip->driver_type == AZX_DRIVER_SKL) {
 556                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 557                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 558                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 559         }
 560         azx_init_chip(chip, full_reset);
 561         if (chip->driver_type == AZX_DRIVER_SKL) {
 562                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 563                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 564                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 565         }
 566
 567         snd_hdac_set_codec_wakeup(bus, false);
 568
 569         /* reduce dma latency to avoid noise */
 570         if (IS_BXT(pci))
 571                 bxt_reduce_dma_latency(chip);
 572
 573         if (bus->mlcap != NULL)
 574                 intel_init_lctl(chip);
 575 }
 576
 577 /* calculate runtime delay from LPIB */
 578 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 579                                    unsigned int pos)
 580 {
 581         struct snd_pcm_substream *substream = azx_dev->core.substream;
 582         int stream = substream->stream;
 583         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 584         int delay;
 585
 586         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 587                 delay = pos - lpib_pos;
 588         else
 589                 delay = lpib_pos - pos;
 590         if (delay < 0) {
 591                 if (delay >= azx_dev->core.delay_negative_threshold)
 592                         delay = 0;
 593                 else
 594                         delay += azx_dev->core.bufsize;
 595         }
 596
 597         if (delay >= azx_dev->core.period_bytes) {
 598                 dev_info(chip->card->dev,
 599                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 600                          delay, azx_dev->core.period_bytes);
 601                 delay = 0;
 602                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 603                 chip->get_delay[stream] = NULL;
 604         }
 605
 606         return bytes_to_frames(substream->runtime, delay);
 607 }
 608
 609 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 610
 611 /* called from IRQ */
 612 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 613 {
 614         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 615         int ok;
 616
 617         ok = azx_position_ok(chip, azx_dev);
 618         if (ok == 1) {
 619                 azx_dev->irq_pending = 0;
 620                 return ok;
 621         } else if (ok == 0) {
 622                 /* bogus IRQ, process it later */
 623                 azx_dev->irq_pending = 1;
 624                 schedule_work(&hda->irq_pending_work);
 625         }
 626         return 0;
 627 }
 628
 629 #define display_power(chip, enable) \
 630         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 631
 632 /*
 633  * Check whether the current DMA position is acceptable for updating
 634  * periods.  Returns non-zero if it's OK.
 635  *
 636  * Many HD-audio controllers appear pretty inaccurate about
 637  * the update-IRQ timing.  The IRQ is issued before actually the
 638  * data is processed.  So, we need to process it afterwords in a
 639  * workqueue.
 640  */
 641 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 642 {
 643         struct snd_pcm_substream *substream = azx_dev->core.substream;
 644         int stream = substream->stream;
 645         u32 wallclk;
 646         unsigned int pos;
 647
 648         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 649         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 650                 return -1;      /* bogus (too early) interrupt */
 651
 652         if (chip->get_position[stream])
 653                 pos = chip->get_position[stream](chip, azx_dev);
 654         else { /* use the position buffer as default */
 655                 pos = azx_get_pos_posbuf(chip, azx_dev);
 656                 if (!pos || pos == (u32)-1) {
 657                         dev_info(chip->card->dev,
 658                                  "Invalid position buffer, using LPIB read method instead.\n");
 659                         chip->get_position[stream] = azx_get_pos_lpib;
 660                         if (chip->get_position[0] == azx_get_pos_lpib &&
 661                             chip->get_position[1] == azx_get_pos_lpib)
 662                                 azx_bus(chip)->use_posbuf = false;
 663                         pos = azx_get_pos_lpib(chip, azx_dev);
 664                         chip->get_delay[stream] = NULL;
 665                 } else {
 666                         chip->get_position[stream] = azx_get_pos_posbuf;
 667                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 668                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 669                 }
 670         }
 671
 672         if (pos >= azx_dev->core.bufsize)
 673                 pos = 0;
 674
 675         if (WARN_ONCE(!azx_dev->core.period_bytes,
 676                       "hda-intel: zero azx_dev->period_bytes"))
 677                 return -1; /* this shouldn't happen! */
 678         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 679             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 680                 /* NG - it's below the first next period boundary */
 681                 return chip->bdl_pos_adj ? 0 : -1;
 682         azx_dev->core.start_wallclk += wallclk;
 683         return 1; /* OK, it's fine */
 684 }
 685
 686 /*
 687  * The work for pending PCM period updates.
 688  */
 689 static void azx_irq_pending_work(struct work_struct *work)
 690 {
 691         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 692         struct azx *chip = &hda->chip;
 693         struct hdac_bus *bus = azx_bus(chip);
 694         struct hdac_stream *s;
 695         int pending, ok;
 696
 697         if (!hda->irq_pending_warned) {
 698                 dev_info(chip->card->dev,
 699                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 700                          chip->card->number);
 701                 hda->irq_pending_warned = 1;
 702         }
 703
 704         for (;;) {
 705                 pending = 0;
 706                 spin_lock_irq(&bus->reg_lock);
 707                 list_for_each_entry(s, &bus->stream_list, list) {
 708                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 709                         if (!azx_dev->irq_pending ||
 710                             !s->substream ||
 711                             !s->running)
 712                                 continue;
 713                         ok = azx_position_ok(chip, azx_dev);
 714                         if (ok > 0) {
 715                                 azx_dev->irq_pending = 0;
 716                                 spin_unlock(&bus->reg_lock);
 717                                 snd_pcm_period_elapsed(s->substream);
 718                                 spin_lock(&bus->reg_lock);
 719                         } else if (ok < 0) {
 720                                 pending = 0;    /* too early */
 721                         } else
 722                                 pending++;
 723                 }
 724                 spin_unlock_irq(&bus->reg_lock);
 725                 if (!pending)
 726                         return;
 727                 msleep(1);
 728         }
 729 }
 730
 731 /* clear irq_pending flags and assure no on-going workq */
 732 static void azx_clear_irq_pending(struct azx *chip)
 733 {
 734         struct hdac_bus *bus = azx_bus(chip);
 735         struct hdac_stream *s;
 736
 737         spin_lock_irq(&bus->reg_lock);
 738         list_for_each_entry(s, &bus->stream_list, list) {
 739                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 740                 azx_dev->irq_pending = 0;
 741         }
 742         spin_unlock_irq(&bus->reg_lock);
 743 }
 744
 745 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 746 {
 747         struct hdac_bus *bus = azx_bus(chip);
 748
 749         if (request_irq(chip->pci->irq, azx_interrupt,
 750                         chip->msi ? 0 : IRQF_SHARED,
 751                         chip->card->irq_descr, chip)) {
 752                 dev_err(chip->card->dev,
 753                         "unable to grab IRQ %d, disabling device\n",
 754                         chip->pci->irq);
 755                 if (do_disconnect)
 756                         snd_card_disconnect(chip->card);
 757                 return -1;
 758         }
 759         bus->irq = chip->pci->irq;
 760         chip->card->sync_irq = bus->irq;
 761         pci_intx(chip->pci, !chip->msi);
 762         return 0;
 763 }
 764
 765 /* get the current DMA position with correction on VIA chips */
 766 static unsigned int azx_via_get_position(struct azx *chip,
 767                                          struct azx_dev *azx_dev)
 768 {
 769         unsigned int link_pos, mini_pos, bound_pos;
 770         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 771         unsigned int fifo_size;
 772
 773         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 774         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 775                 /* Playback, no problem using link position */
 776                 return link_pos;
 777         }
 778
 779         /* Capture */
 780         /* For new chipset,
 781          * use mod to get the DMA position just like old chipset
 782          */
 783         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 784         mod_dma_pos %= azx_dev->core.period_bytes;
 785
 786         fifo_size = azx_stream(azx_dev)->fifo_size - 1;
 787
 788         if (azx_dev->insufficient) {
 789                 /* Link position never gather than FIFO size */
 790                 if (link_pos <= fifo_size)
 791                         return 0;
 792
 793                 azx_dev->insufficient = 0;
 794         }
 795
 796         if (link_pos <= fifo_size)
 797                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 798         else
 799                 mini_pos = link_pos - fifo_size;
 800
 801         /* Find nearest previous boudary */
 802         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 803         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 804         if (mod_link_pos >= fifo_size)
 805                 bound_pos = link_pos - mod_link_pos;
 806         else if (mod_dma_pos >= mod_mini_pos)
 807                 bound_pos = mini_pos - mod_mini_pos;
 808         else {
 809                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 810                 if (bound_pos >= azx_dev->core.bufsize)
 811                         bound_pos = 0;
 812         }
 813
 814         /* Calculate real DMA position we want */
 815         return bound_pos + mod_dma_pos;
 816 }
 817
 818 #define AMD_FIFO_SIZE   32
 819
 820 /* get the current DMA position with FIFO size correction */
 821 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
 822 {
 823         struct snd_pcm_substream *substream = azx_dev->core.substream;
 824         struct snd_pcm_runtime *runtime = substream->runtime;
 825         unsigned int pos, delay;
 826
 827         pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 828         if (!runtime)
 829                 return pos;
 830
 831         runtime->delay = AMD_FIFO_SIZE;
 832         delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
 833         if (azx_dev->insufficient) {
 834                 if (pos < delay) {
 835                         delay = pos;
 836                         runtime->delay = bytes_to_frames(runtime, pos);
 837                 } else {
 838                         azx_dev->insufficient = 0;
 839                 }
 840         }
 841
 842         /* correct the DMA position for capture stream */
 843         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 844                 if (pos < delay)
 845                         pos += azx_dev->core.bufsize;
 846                 pos -= delay;
 847         }
 848
 849         return pos;
 850 }
 851
 852 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
 853                                    unsigned int pos)
 854 {
 855         struct snd_pcm_substream *substream = azx_dev->core.substream;
 856
 857         /* just read back the calculated value in the above */
 858         return substream->runtime->delay;
 859 }
 860
 861 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 862                                          struct azx_dev *azx_dev)
 863 {
 864         return _snd_hdac_chip_readl(azx_bus(chip),
 865                                     AZX_REG_VS_SDXDPIB_XBASE +
 866                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 867                                      azx_dev->core.index));
 868 }
 869
 870 /* get the current DMA position with correction on SKL+ chips */
 871 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 872 {
 873         /* DPIB register gives a more accurate position for playback */
 874         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 875                 return azx_skl_get_dpib_pos(chip, azx_dev);
 876
 877         /* For capture, we need to read posbuf, but it requires a delay
 878          * for the possible boundary overlap; the read of DPIB fetches the
 879          * actual posbuf
 880          */
 881         udelay(20);
 882         azx_skl_get_dpib_pos(chip, azx_dev);
 883         return azx_get_pos_posbuf(chip, azx_dev);
 884 }
 885
 886 #ifdef CONFIG_PM
 887 static DEFINE_MUTEX(card_list_lock);
 888 static LIST_HEAD(card_list);
 889
 890 static void azx_add_card_list(struct azx *chip)
 891 {
 892         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 893         mutex_lock(&card_list_lock);
 894         list_add(&hda->list, &card_list);
 895         mutex_unlock(&card_list_lock);
 896 }
 897
 898 static void azx_del_card_list(struct azx *chip)
 899 {
 900         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 901         mutex_lock(&card_list_lock);
 902         list_del_init(&hda->list);
 903         mutex_unlock(&card_list_lock);
 904 }
 905
 906 /* trigger power-save check at writing parameter */
 907 static int param_set_xint(const char *val, const struct kernel_param *kp)
 908 {
 909         struct hda_intel *hda;
 910         struct azx *chip;
 911         int prev = power_save;
 912         int ret = param_set_int(val, kp);
 913
 914         if (ret || prev == power_save)
 915                 return ret;
 916
 917         mutex_lock(&card_list_lock);
 918         list_for_each_entry(hda, &card_list, list) {
 919                 chip = &hda->chip;
 920                 if (!hda->probe_continued || chip->disabled)
 921                         continue;
 922                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 923         }
 924         mutex_unlock(&card_list_lock);
 925         return 0;
 926 }
 927
 928 /*
 929  * power management
 930  */
 931 static bool azx_is_pm_ready(struct snd_card *card)
 932 {
 933         struct azx *chip;
 934         struct hda_intel *hda;
 935
 936         if (!card)
 937                 return false;
 938         chip = card->private_data;
 939         hda = container_of(chip, struct hda_intel, chip);
 940         if (chip->disabled || hda->init_failed || !chip->running)
 941                 return false;
 942         return true;
 943 }
 944
 945 static void __azx_runtime_suspend(struct azx *chip)
 946 {
 947         azx_stop_chip(chip);
 948         azx_enter_link_reset(chip);
 949         azx_clear_irq_pending(chip);
 950         display_power(chip, false);
 951 }
 952
 953 static void __azx_runtime_resume(struct azx *chip)
 954 {
 955         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 956         struct hdac_bus *bus = azx_bus(chip);
 957         struct hda_codec *codec;
 958         int status;
 959
 960         display_power(chip, true);
 961         if (hda->need_i915_power)
 962                 snd_hdac_i915_set_bclk(bus);
 963
 964         /* Read STATESTS before controller reset */
 965         status = azx_readw(chip, STATESTS);
 966
 967         azx_init_pci(chip);
 968         hda_intel_init_chip(chip, true);
 969
 970         /* Avoid codec resume if runtime resume is for system suspend */
 971         if (!chip->pm_prepared) {
 972                 list_for_each_codec(codec, &chip->bus) {
 973                         if (codec->relaxed_resume)
 974                                 continue;
 975
 976                         if (codec->forced_resume || (status & (1 << codec->addr)))
 977                                 pm_request_resume(hda_codec_dev(codec));
 978                 }
 979         }
 980
 981         /* power down again for link-controlled chips */
 982         if (!hda->need_i915_power)
 983                 display_power(chip, false);
 984 }
 985
 986 #ifdef CONFIG_PM_SLEEP
 987 static int azx_prepare(struct device *dev)
 988 {
 989         struct snd_card *card = dev_get_drvdata(dev);
 990         struct azx *chip;
 991
 992         if (!azx_is_pm_ready(card))
 993                 return 0;
 994
 995         chip = card->private_data;
 996         chip->pm_prepared = 1;
 997         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 998
 999         flush_work(&azx_bus(chip)->unsol_work);
1000
1001         /* HDA controller always requires different WAKEEN for runtime suspend
1002          * and system suspend, so don't use direct-complete here.
1003          */
1004         return 0;
1005 }
1006
1007 static void azx_complete(struct device *dev)
1008 {
1009         struct snd_card *card = dev_get_drvdata(dev);
1010         struct azx *chip;
1011
1012         if (!azx_is_pm_ready(card))
1013                 return;
1014
1015         chip = card->private_data;
1016         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1017         chip->pm_prepared = 0;
1018 }
1019
1020 static int azx_suspend(struct device *dev)
1021 {
1022         struct snd_card *card = dev_get_drvdata(dev);
1023         struct azx *chip;
1024         struct hdac_bus *bus;
1025
1026         if (!azx_is_pm_ready(card))
1027                 return 0;
1028
1029         chip = card->private_data;
1030         bus = azx_bus(chip);
1031         __azx_runtime_suspend(chip);
1032         if (bus->irq >= 0) {
1033                 free_irq(bus->irq, chip);
1034                 bus->irq = -1;
1035                 chip->card->sync_irq = -1;
1036         }
1037
1038         if (chip->msi)
1039                 pci_disable_msi(chip->pci);
1040
1041         trace_azx_suspend(chip);
1042         return 0;
1043 }
1044
1045 static int azx_resume(struct device *dev)
1046 {
1047         struct snd_card *card = dev_get_drvdata(dev);
1048         struct azx *chip;
1049
1050         if (!azx_is_pm_ready(card))
1051                 return 0;
1052
1053         chip = card->private_data;
1054         if (chip->msi)
1055                 if (pci_enable_msi(chip->pci) < 0)
1056                         chip->msi = 0;
1057         if (azx_acquire_irq(chip, 1) < 0)
1058                 return -EIO;
1059
1060         __azx_runtime_resume(chip);
1061
1062         trace_azx_resume(chip);
1063         return 0;
1064 }
1065
1066 /* put codec down to D3 at hibernation for Intel SKL+;
1067  * otherwise BIOS may still access the codec and screw up the driver
1068  */
1069 static int azx_freeze_noirq(struct device *dev)
1070 {
1071         struct snd_card *card = dev_get_drvdata(dev);
1072         struct azx *chip = card->private_data;
1073         struct pci_dev *pci = to_pci_dev(dev);
1074
1075         if (!azx_is_pm_ready(card))
1076                 return 0;
1077         if (chip->driver_type == AZX_DRIVER_SKL)
1078                 pci_set_power_state(pci, PCI_D3hot);
1079
1080         return 0;
1081 }
1082
1083 static int azx_thaw_noirq(struct device *dev)
1084 {
1085         struct snd_card *card = dev_get_drvdata(dev);
1086         struct azx *chip = card->private_data;
1087         struct pci_dev *pci = to_pci_dev(dev);
1088
1089         if (!azx_is_pm_ready(card))
1090                 return 0;
1091         if (chip->driver_type == AZX_DRIVER_SKL)
1092                 pci_set_power_state(pci, PCI_D0);
1093
1094         return 0;
1095 }
1096 #endif /* CONFIG_PM_SLEEP */
1097
1098 static int azx_runtime_suspend(struct device *dev)
1099 {
1100         struct snd_card *card = dev_get_drvdata(dev);
1101         struct azx *chip;
1102
1103         if (!azx_is_pm_ready(card))
1104                 return 0;
1105         chip = card->private_data;
1106
1107         /* enable controller wake up event */
1108         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
1109
1110         __azx_runtime_suspend(chip);
1111         trace_azx_runtime_suspend(chip);
1112         return 0;
1113 }
1114
1115 static int azx_runtime_resume(struct device *dev)
1116 {
1117         struct snd_card *card = dev_get_drvdata(dev);
1118         struct azx *chip;
1119
1120         if (!azx_is_pm_ready(card))
1121                 return 0;
1122         chip = card->private_data;
1123         __azx_runtime_resume(chip);
1124
1125         /* disable controller Wake Up event*/
1126         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
1127
1128         trace_azx_runtime_resume(chip);
1129         return 0;
1130 }
1131
1132 static int azx_runtime_idle(struct device *dev)
1133 {
1134         struct snd_card *card = dev_get_drvdata(dev);
1135         struct azx *chip;
1136         struct hda_intel *hda;
1137
1138         if (!card)
1139                 return 0;
1140
1141         chip = card->private_data;
1142         hda = container_of(chip, struct hda_intel, chip);
1143         if (chip->disabled || hda->init_failed)
1144                 return 0;
1145
1146         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1147             azx_bus(chip)->codec_powered || !chip->running)
1148                 return -EBUSY;
1149
1150         /* ELD notification gets broken when HD-audio bus is off */
1151         if (needs_eld_notify_link(chip))
1152                 return -EBUSY;
1153
1154         return 0;
1155 }
1156
1157 static const struct dev_pm_ops azx_pm = {
1158         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1159 #ifdef CONFIG_PM_SLEEP
1160         .prepare = azx_prepare,
1161         .complete = azx_complete,
1162         .freeze_noirq = azx_freeze_noirq,
1163         .thaw_noirq = azx_thaw_noirq,
1164 #endif
1165         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1166 };
1167
1168 #define AZX_PM_OPS      &azx_pm
1169 #else
1170 #define azx_add_card_list(chip) /* NOP */
1171 #define azx_del_card_list(chip) /* NOP */
1172 #define AZX_PM_OPS      NULL
1173 #endif /* CONFIG_PM */
1174
1175
1176 static int azx_probe_continue(struct azx *chip);
1177
1178 #ifdef SUPPORT_VGA_SWITCHEROO
1179 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1180
1181 static void azx_vs_set_state(struct pci_dev *pci,
1182                              enum vga_switcheroo_state state)
1183 {
1184         struct snd_card *card = pci_get_drvdata(pci);
1185         struct azx *chip = card->private_data;
1186         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1187         struct hda_codec *codec;
1188         bool disabled;
1189
1190         wait_for_completion(&hda->probe_wait);
1191         if (hda->init_failed)
1192                 return;
1193
1194         disabled = (state == VGA_SWITCHEROO_OFF);
1195         if (chip->disabled == disabled)
1196                 return;
1197
1198         if (!hda->probe_continued) {
1199                 chip->disabled = disabled;
1200                 if (!disabled) {
1201                         dev_info(chip->card->dev,
1202                                  "Start delayed initialization\n");
1203                         if (azx_probe_continue(chip) < 0)
1204                                 dev_err(chip->card->dev, "initialization error\n");
1205                 }
1206         } else {
1207                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1208                          disabled ? "Disabling" : "Enabling");
1209                 if (disabled) {
1210                         list_for_each_codec(codec, &chip->bus) {
1211                                 pm_runtime_suspend(hda_codec_dev(codec));
1212                                 pm_runtime_disable(hda_codec_dev(codec));
1213                         }
1214                         pm_runtime_suspend(card->dev);
1215                         pm_runtime_disable(card->dev);
1216                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1217                          * however we have no ACPI handle, so pci/acpi can't put us there,
1218                          * put ourselves there */
1219                         pci->current_state = PCI_D3cold;
1220                         chip->disabled = true;
1221                         if (snd_hda_lock_devices(&chip->bus))
1222                                 dev_warn(chip->card->dev,
1223                                          "Cannot lock devices!\n");
1224                 } else {
1225                         snd_hda_unlock_devices(&chip->bus);
1226                         chip->disabled = false;
1227                         pm_runtime_enable(card->dev);
1228                         list_for_each_codec(codec, &chip->bus) {
1229                                 pm_runtime_enable(hda_codec_dev(codec));
1230                                 pm_runtime_resume(hda_codec_dev(codec));
1231                         }
1232                 }
1233         }
1234 }
1235
1236 static bool azx_vs_can_switch(struct pci_dev *pci)
1237 {
1238         struct snd_card *card = pci_get_drvdata(pci);
1239         struct azx *chip = card->private_data;
1240         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1241
1242         wait_for_completion(&hda->probe_wait);
1243         if (hda->init_failed)
1244                 return false;
1245         if (chip->disabled || !hda->probe_continued)
1246                 return true;
1247         if (snd_hda_lock_devices(&chip->bus))
1248                 return false;
1249         snd_hda_unlock_devices(&chip->bus);
1250         return true;
1251 }
1252
1253 /*
1254  * The discrete GPU cannot power down unless the HDA controller runtime
1255  * suspends, so activate runtime PM on codecs even if power_save == 0.
1256  */
1257 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1258 {
1259         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1260         struct hda_codec *codec;
1261
1262         if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1263                 list_for_each_codec(codec, &chip->bus)
1264                         codec->auto_runtime_pm = 1;
1265                 /* reset the power save setup */
1266                 if (chip->running)
1267                         set_default_power_save(chip);
1268         }
1269 }
1270
1271 static void azx_vs_gpu_bound(struct pci_dev *pci,
1272                              enum vga_switcheroo_client_id client_id)
1273 {
1274         struct snd_card *card = pci_get_drvdata(pci);
1275         struct azx *chip = card->private_data;
1276
1277         if (client_id == VGA_SWITCHEROO_DIS)
1278                 chip->bus.keep_power = 0;
1279         setup_vga_switcheroo_runtime_pm(chip);
1280 }
1281
1282 static void init_vga_switcheroo(struct azx *chip)
1283 {
1284         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1285         struct pci_dev *p = get_bound_vga(chip->pci);
1286         struct pci_dev *parent;
1287         if (p) {
1288                 dev_info(chip->card->dev,
1289                          "Handle vga_switcheroo audio client\n");
1290                 hda->use_vga_switcheroo = 1;
1291
1292                 /* cleared in either gpu_bound op or codec probe, or when its
1293                  * upstream port has _PR3 (i.e. dGPU).
1294                  */
1295                 parent = pci_upstream_bridge(p);
1296                 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1297                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1298                 pci_dev_put(p);
1299         }
1300 }
1301
1302 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1303         .set_gpu_state = azx_vs_set_state,
1304         .can_switch = azx_vs_can_switch,
1305         .gpu_bound = azx_vs_gpu_bound,
1306 };
1307
1308 static int register_vga_switcheroo(struct azx *chip)
1309 {
1310         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1311         struct pci_dev *p;
1312         int err;
1313
1314         if (!hda->use_vga_switcheroo)
1315                 return 0;
1316
1317         p = get_bound_vga(chip->pci);
1318         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1319         pci_dev_put(p);
1320
1321         if (err < 0)
1322                 return err;
1323         hda->vga_switcheroo_registered = 1;
1324
1325         return 0;
1326 }
1327 #else
1328 #define init_vga_switcheroo(chip)               /* NOP */
1329 #define register_vga_switcheroo(chip)           0
1330 #define check_hdmi_disabled(pci)        false
1331 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1332 #endif /* SUPPORT_VGA_SWITCHER */
1333
1334 /*
1335  * destructor
1336  */
1337 static void azx_free(struct azx *chip)
1338 {
1339         struct pci_dev *pci = chip->pci;
1340         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1341         struct hdac_bus *bus = azx_bus(chip);
1342
1343         if (hda->freed)
1344                 return;
1345
1346         if (azx_has_pm_runtime(chip) && chip->running)
1347                 pm_runtime_get_noresume(&pci->dev);
1348         chip->running = 0;
1349
1350         azx_del_card_list(chip);
1351
1352         hda->init_failed = 1; /* to be sure */
1353         complete_all(&hda->probe_wait);
1354
1355         if (use_vga_switcheroo(hda)) {
1356                 if (chip->disabled && hda->probe_continued)
1357                         snd_hda_unlock_devices(&chip->bus);
1358                 if (hda->vga_switcheroo_registered)
1359                         vga_switcheroo_unregister_client(chip->pci);
1360         }
1361
1362         if (bus->chip_init) {
1363                 azx_clear_irq_pending(chip);
1364                 azx_stop_all_streams(chip);
1365                 azx_stop_chip(chip);
1366         }
1367
1368         if (bus->irq >= 0)
1369                 free_irq(bus->irq, (void*)chip);
1370         if (chip->msi)
1371                 pci_disable_msi(chip->pci);
1372         iounmap(bus->remap_addr);
1373
1374         azx_free_stream_pages(chip);
1375         azx_free_streams(chip);
1376         snd_hdac_bus_exit(bus);
1377
1378         if (chip->region_requested)
1379                 pci_release_regions(chip->pci);
1380
1381         pci_disable_device(chip->pci);
1382 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1383         release_firmware(chip->fw);
1384 #endif
1385         display_power(chip, false);
1386
1387         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1388                 snd_hdac_i915_exit(bus);
1389
1390         hda->freed = 1;
1391 }
1392
1393 static int azx_dev_disconnect(struct snd_device *device)
1394 {
1395         struct azx *chip = device->device_data;
1396         struct hdac_bus *bus = azx_bus(chip);
1397
1398         chip->bus.shutdown = 1;
1399         cancel_work_sync(&bus->unsol_work);
1400
1401         return 0;
1402 }
1403
1404 static int azx_dev_free(struct snd_device *device)
1405 {
1406         azx_free(device->device_data);
1407         return 0;
1408 }
1409
1410 #ifdef SUPPORT_VGA_SWITCHEROO
1411 #ifdef CONFIG_ACPI
1412 /* ATPX is in the integrated GPU's namespace */
1413 static bool atpx_present(void)
1414 {
1415         struct pci_dev *pdev = NULL;
1416         acpi_handle dhandle, atpx_handle;
1417         acpi_status status;
1418
1419         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1420                 dhandle = ACPI_HANDLE(&pdev->dev);
1421                 if (dhandle) {
1422                         status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1423                         if (ACPI_SUCCESS(status)) {
1424                                 pci_dev_put(pdev);
1425                                 return true;
1426                         }
1427                 }
1428         }
1429         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
1430                 dhandle = ACPI_HANDLE(&pdev->dev);
1431                 if (dhandle) {
1432                         status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1433                         if (ACPI_SUCCESS(status)) {
1434                                 pci_dev_put(pdev);
1435                                 return true;
1436                         }
1437                 }
1438         }
1439         return false;
1440 }
1441 #else
1442 static bool atpx_present(void)
1443 {
1444         return false;
1445 }
1446 #endif
1447
1448 /*
1449  * Check of disabled HDMI controller by vga_switcheroo
1450  */
1451 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1452 {
1453         struct pci_dev *p;
1454
1455         /* check only discrete GPU */
1456         switch (pci->vendor) {
1457         case PCI_VENDOR_ID_ATI:
1458         case PCI_VENDOR_ID_AMD:
1459                 if (pci->devfn == 1) {
1460                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1461                                                         pci->bus->number, 0);
1462                         if (p) {
1463                                 /* ATPX is in the integrated GPU's ACPI namespace
1464                                  * rather than the dGPU's namespace. However,
1465                                  * the dGPU is the one who is involved in
1466                                  * vgaswitcheroo.
1467                                  */
1468                                 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1469                                     atpx_present())
1470                                         return p;
1471                                 pci_dev_put(p);
1472                         }
1473                 }
1474                 break;
1475         case PCI_VENDOR_ID_NVIDIA:
1476                 if (pci->devfn == 1) {
1477                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1478                                                         pci->bus->number, 0);
1479                         if (p) {
1480                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1481                                         return p;
1482                                 pci_dev_put(p);
1483                         }
1484                 }
1485                 break;
1486         }
1487         return NULL;
1488 }
1489
1490 static bool check_hdmi_disabled(struct pci_dev *pci)
1491 {
1492         bool vga_inactive = false;
1493         struct pci_dev *p = get_bound_vga(pci);
1494
1495         if (p) {
1496                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1497                         vga_inactive = true;
1498                 pci_dev_put(p);
1499         }
1500         return vga_inactive;
1501 }
1502 #endif /* SUPPORT_VGA_SWITCHEROO */
1503
1504 /*
1505  * allow/deny-listing for position_fix
1506  */
1507 static const struct snd_pci_quirk position_fix_list[] = {
1508         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1509         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1510         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1511         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1512         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1513         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1514         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1515         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1516         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1517         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1518         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1519         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1520         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1521         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1522         {}
1523 };
1524
1525 static int check_position_fix(struct azx *chip, int fix)
1526 {
1527         const struct snd_pci_quirk *q;
1528
1529         switch (fix) {
1530         case POS_FIX_AUTO:
1531         case POS_FIX_LPIB:
1532         case POS_FIX_POSBUF:
1533         case POS_FIX_VIACOMBO:
1534         case POS_FIX_COMBO:
1535         case POS_FIX_SKL:
1536         case POS_FIX_FIFO:
1537                 return fix;
1538         }
1539
1540         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1541         if (q) {
1542                 dev_info(chip->card->dev,
1543                          "position_fix set to %d for device %04x:%04x\n",
1544                          q->value, q->subvendor, q->subdevice);
1545                 return q->value;
1546         }
1547
1548         /* Check VIA/ATI HD Audio Controller exist */
1549         if (chip->driver_type == AZX_DRIVER_VIA) {
1550                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1551                 return POS_FIX_VIACOMBO;
1552         }
1553         if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1554                 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1555                 return POS_FIX_FIFO;
1556         }
1557         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1558                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1559                 return POS_FIX_LPIB;
1560         }
1561         if (chip->driver_type == AZX_DRIVER_SKL) {
1562                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1563                 return POS_FIX_SKL;
1564         }
1565         return POS_FIX_AUTO;
1566 }
1567
1568 static void assign_position_fix(struct azx *chip, int fix)
1569 {
1570         static const azx_get_pos_callback_t callbacks[] = {
1571                 [POS_FIX_AUTO] = NULL,
1572                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1573                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1574                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1575                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1576                 [POS_FIX_SKL] = azx_get_pos_skl,
1577                 [POS_FIX_FIFO] = azx_get_pos_fifo,
1578         };
1579
1580         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1581
1582         /* combo mode uses LPIB only for playback */
1583         if (fix == POS_FIX_COMBO)
1584                 chip->get_position[1] = NULL;
1585
1586         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1587             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1588                 chip->get_delay[0] = chip->get_delay[1] =
1589                         azx_get_delay_from_lpib;
1590         }
1591
1592         if (fix == POS_FIX_FIFO)
1593                 chip->get_delay[0] = chip->get_delay[1] =
1594                         azx_get_delay_from_fifo;
1595 }
1596
1597 /*
1598  * deny-lists for probe_mask
1599  */
1600 static const struct snd_pci_quirk probe_mask_list[] = {
1601         /* Thinkpad often breaks the controller communication when accessing
1602          * to the non-working (or non-existing) modem codec slot.
1603          */
1604         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1605         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1606         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1607         /* broken BIOS */
1608         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1609         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1610         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1611         /* forced codec slots */
1612         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1613         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1614         /* WinFast VP200 H (Teradici) user reported broken communication */
1615         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1616         {}
1617 };
1618
1619 #define AZX_FORCE_CODEC_MASK    0x100
1620
1621 static void check_probe_mask(struct azx *chip, int dev)
1622 {
1623         const struct snd_pci_quirk *q;
1624
1625         chip->codec_probe_mask = probe_mask[dev];
1626         if (chip->codec_probe_mask == -1) {
1627                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1628                 if (q) {
1629                         dev_info(chip->card->dev,
1630                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1631                                  q->value, q->subvendor, q->subdevice);
1632                         chip->codec_probe_mask = q->value;
1633                 }
1634         }
1635
1636         /* check forced option */
1637         if (chip->codec_probe_mask != -1 &&
1638             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1639                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1640                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1641                          (int)azx_bus(chip)->codec_mask);
1642         }
1643 }
1644
1645 /*
1646  * allow/deny-list for enable_msi
1647  */
1648 static const struct snd_pci_quirk msi_deny_list[] = {
1649         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1650         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1651         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1652         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1653         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1654         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1655         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1656         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1657         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1658         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1659         {}
1660 };
1661
1662 static void check_msi(struct azx *chip)
1663 {
1664         const struct snd_pci_quirk *q;
1665
1666         if (enable_msi >= 0) {
1667                 chip->msi = !!enable_msi;
1668                 return;
1669         }
1670         chip->msi = 1;  /* enable MSI as default */
1671         q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
1672         if (q) {
1673                 dev_info(chip->card->dev,
1674                          "msi for device %04x:%04x set to %d\n",
1675                          q->subvendor, q->subdevice, q->value);
1676                 chip->msi = q->value;
1677                 return;
1678         }
1679
1680         /* NVidia chipsets seem to cause troubles with MSI */
1681         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1682                 dev_info(chip->card->dev, "Disabling MSI\n");
1683                 chip->msi = 0;
1684         }
1685 }
1686
1687 /* check the snoop mode availability */
1688 static void azx_check_snoop_available(struct azx *chip)
1689 {
1690         int snoop = hda_snoop;
1691
1692         if (snoop >= 0) {
1693                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1694                          snoop ? "snoop" : "non-snoop");
1695                 chip->snoop = snoop;
1696                 chip->uc_buffer = !snoop;
1697                 return;
1698         }
1699
1700         snoop = true;
1701         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1702             chip->driver_type == AZX_DRIVER_VIA) {
1703                 /* force to non-snoop mode for a new VIA controller
1704                  * when BIOS is set
1705                  */
1706                 u8 val;
1707                 pci_read_config_byte(chip->pci, 0x42, &val);
1708                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1709                                       chip->pci->revision == 0x20))
1710                         snoop = false;
1711         }
1712
1713         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1714                 snoop = false;
1715
1716         chip->snoop = snoop;
1717         if (!snoop) {
1718                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1719                 /* C-Media requires non-cached pages only for CORB/RIRB */
1720                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1721                         chip->uc_buffer = true;
1722         }
1723 }
1724
1725 static void azx_probe_work(struct work_struct *work)
1726 {
1727         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1728         azx_probe_continue(&hda->chip);
1729 }
1730
1731 static int default_bdl_pos_adj(struct azx *chip)
1732 {
1733         /* some exceptions: Atoms seem problematic with value 1 */
1734         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1735                 switch (chip->pci->device) {
1736                 case 0x0f04: /* Baytrail */
1737                 case 0x2284: /* Braswell */
1738                         return 32;
1739                 }
1740         }
1741
1742         switch (chip->driver_type) {
1743         case AZX_DRIVER_ICH:
1744         case AZX_DRIVER_PCH:
1745                 return 1;
1746         default:
1747                 return 32;
1748         }
1749 }
1750
1751 /*
1752  * constructor
1753  */
1754 static const struct hda_controller_ops pci_hda_ops;
1755
1756 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1757                       int dev, unsigned int driver_caps,
1758                       struct azx **rchip)
1759 {
1760         static const struct snd_device_ops ops = {
1761                 .dev_disconnect = azx_dev_disconnect,
1762                 .dev_free = azx_dev_free,
1763         };
1764         struct hda_intel *hda;
1765         struct azx *chip;
1766         int err;
1767
1768         *rchip = NULL;
1769
1770         err = pci_enable_device(pci);
1771         if (err < 0)
1772                 return err;
1773
1774         hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1775         if (!hda) {
1776                 pci_disable_device(pci);
1777                 return -ENOMEM;
1778         }
1779
1780         chip = &hda->chip;
1781         mutex_init(&chip->open_mutex);
1782         chip->card = card;
1783         chip->pci = pci;
1784         chip->ops = &pci_hda_ops;
1785         chip->driver_caps = driver_caps;
1786         chip->driver_type = driver_caps & 0xff;
1787         check_msi(chip);
1788         chip->dev_index = dev;
1789         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1790                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1791         INIT_LIST_HEAD(&chip->pcm_list);
1792         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1793         INIT_LIST_HEAD(&hda->list);
1794         init_vga_switcheroo(chip);
1795         init_completion(&hda->probe_wait);
1796
1797         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1798
1799         check_probe_mask(chip, dev);
1800
1801         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1802                 chip->fallback_to_single_cmd = 1;
1803         else /* explicitly set to single_cmd or not */
1804                 chip->single_cmd = single_cmd;
1805
1806         azx_check_snoop_available(chip);
1807
1808         if (bdl_pos_adj[dev] < 0)
1809                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1810         else
1811                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1812
1813         err = azx_bus_init(chip, model[dev]);
1814         if (err < 0) {
1815                 pci_disable_device(pci);
1816                 return err;
1817         }
1818
1819         /* use the non-cached pages in non-snoop mode */
1820         if (!azx_snoop(chip))
1821                 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1822
1823         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1824                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1825                 chip->bus.core.needs_damn_long_delay = 1;
1826         }
1827
1828         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1829         if (err < 0) {
1830                 dev_err(card->dev, "Error creating device [card]!\n");
1831                 azx_free(chip);
1832                 return err;
1833         }
1834
1835         /* continue probing in work context as may trigger request module */
1836         INIT_WORK(&hda->probe_work, azx_probe_work);
1837
1838         *rchip = chip;
1839
1840         return 0;
1841 }
1842
1843 static int azx_first_init(struct azx *chip)
1844 {
1845         int dev = chip->dev_index;
1846         struct pci_dev *pci = chip->pci;
1847         struct snd_card *card = chip->card;
1848         struct hdac_bus *bus = azx_bus(chip);
1849         int err;
1850         unsigned short gcap;
1851         unsigned int dma_bits = 64;
1852
1853 #if BITS_PER_LONG != 64
1854         /* Fix up base address on ULI M5461 */
1855         if (chip->driver_type == AZX_DRIVER_ULI) {
1856                 u16 tmp3;
1857                 pci_read_config_word(pci, 0x40, &tmp3);
1858                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1859                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1860         }
1861 #endif
1862
1863         err = pci_request_regions(pci, "ICH HD audio");
1864         if (err < 0)
1865                 return err;
1866         chip->region_requested = 1;
1867
1868         bus->addr = pci_resource_start(pci, 0);
1869         bus->remap_addr = pci_ioremap_bar(pci, 0);
1870         if (bus->remap_addr == NULL) {
1871                 dev_err(card->dev, "ioremap error\n");
1872                 return -ENXIO;
1873         }
1874
1875         if (chip->driver_type == AZX_DRIVER_SKL)
1876                 snd_hdac_bus_parse_capabilities(bus);
1877
1878         /*
1879          * Some Intel CPUs has always running timer (ART) feature and
1880          * controller may have Global time sync reporting capability, so
1881          * check both of these before declaring synchronized time reporting
1882          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1883          */
1884         chip->gts_present = false;
1885
1886 #ifdef CONFIG_X86
1887         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1888                 chip->gts_present = true;
1889 #endif
1890
1891         if (chip->msi) {
1892                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1893                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1894                         pci->no_64bit_msi = true;
1895                 }
1896                 if (pci_enable_msi(pci) < 0)
1897                         chip->msi = 0;
1898         }
1899
1900         pci_set_master(pci);
1901
1902         gcap = azx_readw(chip, GCAP);
1903         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1904
1905         /* AMD devices support 40 or 48bit DMA, take the safe one */
1906         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1907                 dma_bits = 40;
1908
1909         /* disable SB600 64bit support for safety */
1910         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1911                 struct pci_dev *p_smbus;
1912                 dma_bits = 40;
1913                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1914                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1915                                          NULL);
1916                 if (p_smbus) {
1917                         if (p_smbus->revision < 0x30)
1918                                 gcap &= ~AZX_GCAP_64OK;
1919                         pci_dev_put(p_smbus);
1920                 }
1921         }
1922
1923         /* NVidia hardware normally only supports up to 40 bits of DMA */
1924         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1925                 dma_bits = 40;
1926
1927         /* disable 64bit DMA address on some devices */
1928         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1929                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1930                 gcap &= ~AZX_GCAP_64OK;
1931         }
1932
1933         /* disable buffer size rounding to 128-byte multiples if supported */
1934         if (align_buffer_size >= 0)
1935                 chip->align_buffer_size = !!align_buffer_size;
1936         else {
1937                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1938                         chip->align_buffer_size = 0;
1939                 else
1940                         chip->align_buffer_size = 1;
1941         }
1942
1943         /* allow 64bit DMA address if supported by H/W */
1944         if (!(gcap & AZX_GCAP_64OK))
1945                 dma_bits = 32;
1946         if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1947                 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
1948
1949         /* read number of streams from GCAP register instead of using
1950          * hardcoded value
1951          */
1952         chip->capture_streams = (gcap >> 8) & 0x0f;
1953         chip->playback_streams = (gcap >> 12) & 0x0f;
1954         if (!chip->playback_streams && !chip->capture_streams) {
1955                 /* gcap didn't give any info, switching to old method */
1956
1957                 switch (chip->driver_type) {
1958                 case AZX_DRIVER_ULI:
1959                         chip->playback_streams = ULI_NUM_PLAYBACK;
1960                         chip->capture_streams = ULI_NUM_CAPTURE;
1961                         break;
1962                 case AZX_DRIVER_ATIHDMI:
1963                 case AZX_DRIVER_ATIHDMI_NS:
1964                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1965                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1966                         break;
1967                 case AZX_DRIVER_GENERIC:
1968                 default:
1969                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1970                         chip->capture_streams = ICH6_NUM_CAPTURE;
1971                         break;
1972                 }
1973         }
1974         chip->capture_index_offset = 0;
1975         chip->playback_index_offset = chip->capture_streams;
1976         chip->num_streams = chip->playback_streams + chip->capture_streams;
1977
1978         /* sanity check for the SDxCTL.STRM field overflow */
1979         if (chip->num_streams > 15 &&
1980             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1981                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1982                          "forcing separate stream tags", chip->num_streams);
1983                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1984         }
1985
1986         /* initialize streams */
1987         err = azx_init_streams(chip);
1988         if (err < 0)
1989                 return err;
1990
1991         err = azx_alloc_stream_pages(chip);
1992         if (err < 0)
1993                 return err;
1994
1995         /* initialize chip */
1996         azx_init_pci(chip);
1997
1998         snd_hdac_i915_set_bclk(bus);
1999
2000         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2001
2002         /* codec detection */
2003         if (!azx_bus(chip)->codec_mask) {
2004                 dev_err(card->dev, "no codecs found!\n");
2005                 /* keep running the rest for the runtime PM */
2006         }
2007
2008         if (azx_acquire_irq(chip, 0) < 0)
2009                 return -EBUSY;
2010
2011         strcpy(card->driver, "HDA-Intel");
2012         strscpy(card->shortname, driver_short_names[chip->driver_type],
2013                 sizeof(card->shortname));
2014         snprintf(card->longname, sizeof(card->longname),
2015                  "%s at 0x%lx irq %i",
2016                  card->shortname, bus->addr, bus->irq);
2017
2018         return 0;
2019 }
2020
2021 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2022 /* callback from request_firmware_nowait() */
2023 static void azx_firmware_cb(const struct firmware *fw, void *context)
2024 {
2025         struct snd_card *card = context;
2026         struct azx *chip = card->private_data;
2027
2028         if (fw)
2029                 chip->fw = fw;
2030         else
2031                 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2032         if (!chip->disabled) {
2033                 /* continue probing */
2034                 azx_probe_continue(chip);
2035         }
2036 }
2037 #endif
2038
2039 static int disable_msi_reset_irq(struct azx *chip)
2040 {
2041         struct hdac_bus *bus = azx_bus(chip);
2042         int err;
2043
2044         free_irq(bus->irq, chip);
2045         bus->irq = -1;
2046         chip->card->sync_irq = -1;
2047         pci_disable_msi(chip->pci);
2048         chip->msi = 0;
2049         err = azx_acquire_irq(chip, 1);
2050         if (err < 0)
2051                 return err;
2052
2053         return 0;
2054 }
2055
2056 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2057                              struct vm_area_struct *area)
2058 {
2059 #ifdef CONFIG_X86
2060         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2061         struct azx *chip = apcm->chip;
2062         if (chip->uc_buffer)
2063                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2064 #endif
2065 }
2066
2067 /* Denylist for skipping the whole probe:
2068  * some HD-audio PCI entries are exposed without any codecs, and such devices
2069  * should be ignored from the beginning.
2070  */
2071 static const struct pci_device_id driver_denylist[] = {
2072         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2073         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2074         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2075         {}
2076 };
2077
2078 static const struct hda_controller_ops pci_hda_ops = {
2079         .disable_msi_reset_irq = disable_msi_reset_irq,
2080         .pcm_mmap_prepare = pcm_mmap_prepare,
2081         .position_check = azx_position_check,
2082 };
2083
2084 static int azx_probe(struct pci_dev *pci,
2085                      const struct pci_device_id *pci_id)
2086 {
2087         static int dev;
2088         struct snd_card *card;
2089         struct hda_intel *hda;
2090         struct azx *chip;
2091         bool schedule_probe;
2092         int err;
2093
2094         if (pci_match_id(driver_denylist, pci)) {
2095                 dev_info(&pci->dev, "Skipping the device on the denylist\n");
2096                 return -ENODEV;
2097         }
2098
2099         if (dev >= SNDRV_CARDS)
2100                 return -ENODEV;
2101         if (!enable[dev]) {
2102                 dev++;
2103                 return -ENOENT;
2104         }
2105
2106         /*
2107          * stop probe if another Intel's DSP driver should be activated
2108          */
2109         if (dmic_detect) {
2110                 err = snd_intel_dsp_driver_probe(pci);
2111                 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2112                         dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
2113                         return -ENODEV;
2114                 }
2115         } else {
2116                 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2117         }
2118
2119         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2120                            0, &card);
2121         if (err < 0) {
2122                 dev_err(&pci->dev, "Error creating card!\n");
2123                 return err;
2124         }
2125
2126         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2127         if (err < 0)
2128                 goto out_free;
2129         card->private_data = chip;
2130         hda = container_of(chip, struct hda_intel, chip);
2131
2132         pci_set_drvdata(pci, card);
2133
2134         err = register_vga_switcheroo(chip);
2135         if (err < 0) {
2136                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2137                 goto out_free;
2138         }
2139
2140         if (check_hdmi_disabled(pci)) {
2141                 dev_info(card->dev, "VGA controller is disabled\n");
2142                 dev_info(card->dev, "Delaying initialization\n");
2143                 chip->disabled = true;
2144         }
2145
2146         schedule_probe = !chip->disabled;
2147
2148 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2149         if (patch[dev] && *patch[dev]) {
2150                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2151                          patch[dev]);
2152                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2153                                               &pci->dev, GFP_KERNEL, card,
2154                                               azx_firmware_cb);
2155                 if (err < 0)
2156                         goto out_free;
2157                 schedule_probe = false; /* continued in azx_firmware_cb() */
2158         }
2159 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2160
2161 #ifndef CONFIG_SND_HDA_I915
2162         if (CONTROLLER_IN_GPU(pci))
2163                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2164 #endif
2165
2166         if (schedule_probe)
2167                 schedule_work(&hda->probe_work);
2168
2169         dev++;
2170         if (chip->disabled)
2171                 complete_all(&hda->probe_wait);
2172         return 0;
2173
2174 out_free:
2175         snd_card_free(card);
2176         return err;
2177 }
2178
2179 #ifdef CONFIG_PM
2180 /* On some boards setting power_save to a non 0 value leads to clicking /
2181  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2182  * figure out how to avoid these sounds, but that is not always feasible.
2183  * So we keep a list of devices where we disable powersaving as its known
2184  * to causes problems on these devices.
2185  */
2186 static const struct snd_pci_quirk power_save_denylist[] = {
2187         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2188         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2189         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2190         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2191         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2192         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2193         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2194         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2195         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2196         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2197         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2198         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2199         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2200         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2201         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2202         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2203         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2204         /* https://bugs.launchpad.net/bugs/1821663 */
2205         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2206         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2207         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2208         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2209         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2210         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2211         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2212         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2213         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2214         /* https://bugs.launchpad.net/bugs/1821663 */
2215         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2216         {}
2217 };
2218 #endif /* CONFIG_PM */
2219
2220 static void set_default_power_save(struct azx *chip)
2221 {
2222         int val = power_save;
2223
2224 #ifdef CONFIG_PM
2225         if (pm_blacklist) {
2226                 const struct snd_pci_quirk *q;
2227
2228                 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
2229                 if (q && val) {
2230                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
2231                                  q->subvendor, q->subdevice);
2232                         val = 0;
2233                 }
2234         }
2235 #endif /* CONFIG_PM */
2236         snd_hda_set_power_save(&chip->bus, val * 1000);
2237 }
2238
2239 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2240 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2241         [AZX_DRIVER_NVIDIA] = 8,
2242         [AZX_DRIVER_TERA] = 1,
2243 };
2244
2245 static int azx_probe_continue(struct azx *chip)
2246 {
2247         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2248         struct hdac_bus *bus = azx_bus(chip);
2249         struct pci_dev *pci = chip->pci;
2250         int dev = chip->dev_index;
2251         int err;
2252
2253         to_hda_bus(bus)->bus_probing = 1;
2254         hda->probe_continued = 1;
2255
2256         /* bind with i915 if needed */
2257         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2258                 err = snd_hdac_i915_init(bus);
2259                 if (err < 0) {
2260                         /* if the controller is bound only with HDMI/DP
2261                          * (for HSW and BDW), we need to abort the probe;
2262                          * for other chips, still continue probing as other
2263                          * codecs can be on the same link.
2264                          */
2265                         if (CONTROLLER_IN_GPU(pci)) {
2266                                 dev_err(chip->card->dev,
2267                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2268                                 goto out_free;
2269                         } else {
2270                                 /* don't bother any longer */
2271                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2272                         }
2273                 }
2274
2275                 /* HSW/BDW controllers need this power */
2276                 if (CONTROLLER_IN_GPU(pci))
2277                         hda->need_i915_power = true;
2278         }
2279
2280         /* Request display power well for the HDA controller or codec. For
2281          * Haswell/Broadwell, both the display HDA controller and codec need
2282          * this power. For other platforms, like Baytrail/Braswell, only the
2283          * display codec needs the power and it can be released after probe.
2284          */
2285         display_power(chip, true);
2286
2287         err = azx_first_init(chip);
2288         if (err < 0)
2289                 goto out_free;
2290
2291 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2292         chip->beep_mode = beep_mode[dev];
2293 #endif
2294
2295         /* create codec instances */
2296         if (bus->codec_mask) {
2297                 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2298                 if (err < 0)
2299                         goto out_free;
2300         }
2301
2302 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2303         if (chip->fw) {
2304                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2305                                          chip->fw->data);
2306                 if (err < 0)
2307                         goto out_free;
2308 #ifndef CONFIG_PM
2309                 release_firmware(chip->fw); /* no longer needed */
2310                 chip->fw = NULL;
2311 #endif
2312         }
2313 #endif
2314         if (bus->codec_mask && !(probe_only[dev] & 1)) {
2315                 err = azx_codec_configure(chip);
2316                 if (err < 0)
2317                         goto out_free;
2318         }
2319
2320         err = snd_card_register(chip->card);
2321         if (err < 0)
2322                 goto out_free;
2323
2324         setup_vga_switcheroo_runtime_pm(chip);
2325
2326         chip->running = 1;
2327         azx_add_card_list(chip);
2328
2329         set_default_power_save(chip);
2330
2331         if (azx_has_pm_runtime(chip)) {
2332                 pm_runtime_use_autosuspend(&pci->dev);
2333                 pm_runtime_allow(&pci->dev);
2334                 pm_runtime_put_autosuspend(&pci->dev);
2335         }
2336
2337 out_free:
2338         if (err < 0) {
2339                 azx_free(chip);
2340                 return err;
2341         }
2342
2343         if (!hda->need_i915_power)
2344                 display_power(chip, false);
2345         complete_all(&hda->probe_wait);
2346         to_hda_bus(bus)->bus_probing = 0;
2347         return 0;
2348 }
2349
2350 static void azx_remove(struct pci_dev *pci)
2351 {
2352         struct snd_card *card = pci_get_drvdata(pci);
2353         struct azx *chip;
2354         struct hda_intel *hda;
2355
2356         if (card) {
2357                 /* cancel the pending probing work */
2358                 chip = card->private_data;
2359                 hda = container_of(chip, struct hda_intel, chip);
2360                 /* FIXME: below is an ugly workaround.
2361                  * Both device_release_driver() and driver_probe_device()
2362                  * take *both* the device's and its parent's lock before
2363                  * calling the remove() and probe() callbacks.  The codec
2364                  * probe takes the locks of both the codec itself and its
2365                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2366                  * the PCI controller is unbound, it takes its lock, too
2367                  * ==> ouch, a deadlock!
2368                  * As a workaround, we unlock temporarily here the controller
2369                  * device during cancel_work_sync() call.
2370                  */
2371                 device_unlock(&pci->dev);
2372                 cancel_work_sync(&hda->probe_work);
2373                 device_lock(&pci->dev);
2374
2375                 snd_card_free(card);
2376         }
2377 }
2378
2379 static void azx_shutdown(struct pci_dev *pci)
2380 {
2381         struct snd_card *card = pci_get_drvdata(pci);
2382         struct azx *chip;
2383
2384         if (!card)
2385                 return;
2386         chip = card->private_data;
2387         if (chip && chip->running)
2388                 azx_stop_chip(chip);
2389 }
2390
2391 /* PCI IDs */
2392 static const struct pci_device_id azx_ids[] = {
2393         /* CPT */
2394         { PCI_DEVICE(0x8086, 0x1c20),
2395           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2396         /* PBG */
2397         { PCI_DEVICE(0x8086, 0x1d20),
2398           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2399         /* Panther Point */
2400         { PCI_DEVICE(0x8086, 0x1e20),
2401           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2402         /* Lynx Point */
2403         { PCI_DEVICE(0x8086, 0x8c20),
2404           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2405         /* 9 Series */
2406         { PCI_DEVICE(0x8086, 0x8ca0),
2407           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2408         /* Wellsburg */
2409         { PCI_DEVICE(0x8086, 0x8d20),
2410           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2411         { PCI_DEVICE(0x8086, 0x8d21),
2412           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2413         /* Lewisburg */
2414         { PCI_DEVICE(0x8086, 0xa1f0),
2415           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2416         { PCI_DEVICE(0x8086, 0xa270),
2417           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2418         /* Lynx Point-LP */
2419         { PCI_DEVICE(0x8086, 0x9c20),
2420           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2421         /* Lynx Point-LP */
2422         { PCI_DEVICE(0x8086, 0x9c21),
2423           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2424         /* Wildcat Point-LP */
2425         { PCI_DEVICE(0x8086, 0x9ca0),
2426           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2427         /* Sunrise Point */
2428         { PCI_DEVICE(0x8086, 0xa170),
2429           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2430         /* Sunrise Point-LP */
2431         { PCI_DEVICE(0x8086, 0x9d70),
2432           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2433         /* Kabylake */
2434         { PCI_DEVICE(0x8086, 0xa171),
2435           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2436         /* Kabylake-LP */
2437         { PCI_DEVICE(0x8086, 0x9d71),
2438           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2439         /* Kabylake-H */
2440         { PCI_DEVICE(0x8086, 0xa2f0),
2441           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2442         /* Coffelake */
2443         { PCI_DEVICE(0x8086, 0xa348),
2444           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2445         /* Cannonlake */
2446         { PCI_DEVICE(0x8086, 0x9dc8),
2447           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2448         /* CometLake-LP */
2449         { PCI_DEVICE(0x8086, 0x02C8),
2450           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2451         /* CometLake-H */
2452         { PCI_DEVICE(0x8086, 0x06C8),
2453           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2454         { PCI_DEVICE(0x8086, 0xf1c8),
2455           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2456         /* CometLake-S */
2457         { PCI_DEVICE(0x8086, 0xa3f0),
2458           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2459         /* CometLake-R */
2460         { PCI_DEVICE(0x8086, 0xf0c8),
2461           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2462         /* Icelake */
2463         { PCI_DEVICE(0x8086, 0x34c8),
2464           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2465         /* Icelake-H */
2466         { PCI_DEVICE(0x8086, 0x3dc8),
2467           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2468         /* Jasperlake */
2469         { PCI_DEVICE(0x8086, 0x38c8),
2470           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2471         { PCI_DEVICE(0x8086, 0x4dc8),
2472           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2473         /* Tigerlake */
2474         { PCI_DEVICE(0x8086, 0xa0c8),
2475           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2476         /* Tigerlake-H */
2477         { PCI_DEVICE(0x8086, 0x43c8),
2478           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2479         /* DG1 */
2480         { PCI_DEVICE(0x8086, 0x490d),
2481           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2482         /* Alderlake-S */
2483         { PCI_DEVICE(0x8086, 0x7ad0),
2484           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2485         /* Alderlake-P */
2486         { PCI_DEVICE(0x8086, 0x51c8),
2487           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2488         /* Alderlake-M */
2489         { PCI_DEVICE(0x8086, 0x51cc),
2490           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2491         /* Elkhart Lake */
2492         { PCI_DEVICE(0x8086, 0x4b55),
2493           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2494         { PCI_DEVICE(0x8086, 0x4b58),
2495           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2496         /* Broxton-P(Apollolake) */
2497         { PCI_DEVICE(0x8086, 0x5a98),
2498           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2499         /* Broxton-T */
2500         { PCI_DEVICE(0x8086, 0x1a98),
2501           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2502         /* Gemini-Lake */
2503         { PCI_DEVICE(0x8086, 0x3198),
2504           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2505         /* Haswell */
2506         { PCI_DEVICE(0x8086, 0x0a0c),
2507           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2508         { PCI_DEVICE(0x8086, 0x0c0c),
2509           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2510         { PCI_DEVICE(0x8086, 0x0d0c),
2511           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2512         /* Broadwell */
2513         { PCI_DEVICE(0x8086, 0x160c),
2514           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2515         /* 5 Series/3400 */
2516         { PCI_DEVICE(0x8086, 0x3b56),
2517           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2518         /* Poulsbo */
2519         { PCI_DEVICE(0x8086, 0x811b),
2520           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2521         /* Oaktrail */
2522         { PCI_DEVICE(0x8086, 0x080a),
2523           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2524         /* BayTrail */
2525         { PCI_DEVICE(0x8086, 0x0f04),
2526           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2527         /* Braswell */
2528         { PCI_DEVICE(0x8086, 0x2284),
2529           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2530         /* ICH6 */
2531         { PCI_DEVICE(0x8086, 0x2668),
2532           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2533         /* ICH7 */
2534         { PCI_DEVICE(0x8086, 0x27d8),
2535           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2536         /* ESB2 */
2537         { PCI_DEVICE(0x8086, 0x269a),
2538           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2539         /* ICH8 */
2540         { PCI_DEVICE(0x8086, 0x284b),
2541           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2542         /* ICH9 */
2543         { PCI_DEVICE(0x8086, 0x293e),
2544           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2545         /* ICH9 */
2546         { PCI_DEVICE(0x8086, 0x293f),
2547           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2548         /* ICH10 */
2549         { PCI_DEVICE(0x8086, 0x3a3e),
2550           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2551         /* ICH10 */
2552         { PCI_DEVICE(0x8086, 0x3a6e),
2553           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2554         /* Generic Intel */
2555         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2556           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2557           .class_mask = 0xffffff,
2558           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2559         /* ATI SB 450/600/700/800/900 */
2560         { PCI_DEVICE(0x1002, 0x437b),
2561           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2562         { PCI_DEVICE(0x1002, 0x4383),
2563           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2564         /* AMD Hudson */
2565         { PCI_DEVICE(0x1022, 0x780d),
2566           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2567         /* AMD, X370 & co */
2568         { PCI_DEVICE(0x1022, 0x1457),
2569           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2570         /* AMD, X570 & co */
2571         { PCI_DEVICE(0x1022, 0x1487),
2572           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2573         /* AMD Stoney */
2574         { PCI_DEVICE(0x1022, 0x157a),
2575           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2576                          AZX_DCAPS_PM_RUNTIME },
2577         /* AMD Raven */
2578         { PCI_DEVICE(0x1022, 0x15e3),
2579           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2580         /* ATI HDMI */
2581         { PCI_DEVICE(0x1002, 0x0002),
2582           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2583           AZX_DCAPS_PM_RUNTIME },
2584         { PCI_DEVICE(0x1002, 0x1308),
2585           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2586         { PCI_DEVICE(0x1002, 0x157a),
2587           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2588         { PCI_DEVICE(0x1002, 0x15b3),
2589           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2590         { PCI_DEVICE(0x1002, 0x793b),
2591           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2592         { PCI_DEVICE(0x1002, 0x7919),
2593           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2594         { PCI_DEVICE(0x1002, 0x960f),
2595           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2596         { PCI_DEVICE(0x1002, 0x970f),
2597           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2598         { PCI_DEVICE(0x1002, 0x9840),
2599           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2600         { PCI_DEVICE(0x1002, 0xaa00),
2601           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2602         { PCI_DEVICE(0x1002, 0xaa08),
2603           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2604         { PCI_DEVICE(0x1002, 0xaa10),
2605           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2606         { PCI_DEVICE(0x1002, 0xaa18),
2607           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2608         { PCI_DEVICE(0x1002, 0xaa20),
2609           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2610         { PCI_DEVICE(0x1002, 0xaa28),
2611           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2612         { PCI_DEVICE(0x1002, 0xaa30),
2613           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2614         { PCI_DEVICE(0x1002, 0xaa38),
2615           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2616         { PCI_DEVICE(0x1002, 0xaa40),
2617           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2618         { PCI_DEVICE(0x1002, 0xaa48),
2619           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2620         { PCI_DEVICE(0x1002, 0xaa50),
2621           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2622         { PCI_DEVICE(0x1002, 0xaa58),
2623           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2624         { PCI_DEVICE(0x1002, 0xaa60),
2625           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2626         { PCI_DEVICE(0x1002, 0xaa68),
2627           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2628         { PCI_DEVICE(0x1002, 0xaa80),
2629           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2630         { PCI_DEVICE(0x1002, 0xaa88),
2631           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2632         { PCI_DEVICE(0x1002, 0xaa90),
2633           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2634         { PCI_DEVICE(0x1002, 0xaa98),
2635           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2636         { PCI_DEVICE(0x1002, 0x9902),
2637           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2638         { PCI_DEVICE(0x1002, 0xaaa0),
2639           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2640         { PCI_DEVICE(0x1002, 0xaaa8),
2641           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2642         { PCI_DEVICE(0x1002, 0xaab0),
2643           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2644         { PCI_DEVICE(0x1002, 0xaac0),
2645           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2646           AZX_DCAPS_PM_RUNTIME },
2647         { PCI_DEVICE(0x1002, 0xaac8),
2648           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2649           AZX_DCAPS_PM_RUNTIME },
2650         { PCI_DEVICE(0x1002, 0xaad8),
2651           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2652           AZX_DCAPS_PM_RUNTIME },
2653         { PCI_DEVICE(0x1002, 0xaae0),
2654           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2655           AZX_DCAPS_PM_RUNTIME },
2656         { PCI_DEVICE(0x1002, 0xaae8),
2657           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2658           AZX_DCAPS_PM_RUNTIME },
2659         { PCI_DEVICE(0x1002, 0xaaf0),
2660           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2661           AZX_DCAPS_PM_RUNTIME },
2662         { PCI_DEVICE(0x1002, 0xaaf8),
2663           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2664           AZX_DCAPS_PM_RUNTIME },
2665         { PCI_DEVICE(0x1002, 0xab00),
2666           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2667           AZX_DCAPS_PM_RUNTIME },
2668         { PCI_DEVICE(0x1002, 0xab08),
2669           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2670           AZX_DCAPS_PM_RUNTIME },
2671         { PCI_DEVICE(0x1002, 0xab10),
2672           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2673           AZX_DCAPS_PM_RUNTIME },
2674         { PCI_DEVICE(0x1002, 0xab18),
2675           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2676           AZX_DCAPS_PM_RUNTIME },
2677         { PCI_DEVICE(0x1002, 0xab20),
2678           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2679           AZX_DCAPS_PM_RUNTIME },
2680         { PCI_DEVICE(0x1002, 0xab28),
2681           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2682           AZX_DCAPS_PM_RUNTIME },
2683         { PCI_DEVICE(0x1002, 0xab38),
2684           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2685           AZX_DCAPS_PM_RUNTIME },
2686         /* VIA VT8251/VT8237A */
2687         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2688         /* VIA GFX VT7122/VX900 */
2689         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2690         /* VIA GFX VT6122/VX11 */
2691         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2692         /* SIS966 */
2693         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2694         /* ULI M5461 */
2695         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2696         /* NVIDIA MCP */
2697         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2698           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2699           .class_mask = 0xffffff,
2700           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2701         /* Teradici */
2702         { PCI_DEVICE(0x6549, 0x1200),
2703           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2704         { PCI_DEVICE(0x6549, 0x2200),
2705           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2706         /* Creative X-Fi (CA0110-IBG) */
2707         /* CTHDA chips */
2708         { PCI_DEVICE(0x1102, 0x0010),
2709           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2710         { PCI_DEVICE(0x1102, 0x0012),
2711           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2712 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2713         /* the following entry conflicts with snd-ctxfi driver,
2714          * as ctxfi driver mutates from HD-audio to native mode with
2715          * a special command sequence.
2716          */
2717         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2718           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2719           .class_mask = 0xffffff,
2720           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2721           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2722 #else
2723         /* this entry seems still valid -- i.e. without emu20kx chip */
2724         { PCI_DEVICE(0x1102, 0x0009),
2725           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2726           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2727 #endif
2728         /* CM8888 */
2729         { PCI_DEVICE(0x13f6, 0x5011),
2730           .driver_data = AZX_DRIVER_CMEDIA |
2731           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2732         /* Vortex86MX */
2733         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2734         /* VMware HDAudio */
2735         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2736         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2737         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2738           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2739           .class_mask = 0xffffff,
2740           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2741         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2742           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2743           .class_mask = 0xffffff,
2744           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2745         /* Zhaoxin */
2746         { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2747         { 0, }
2748 };
2749 MODULE_DEVICE_TABLE(pci, azx_ids);
2750
2751 /* pci_driver definition */
2752 static struct pci_driver azx_driver = {
2753         .name = KBUILD_MODNAME,
2754         .id_table = azx_ids,
2755         .probe = azx_probe,
2756         .remove = azx_remove,
2757         .shutdown = azx_shutdown,
2758         .driver = {
2759                 .pm = AZX_PM_OPS,
2760         },
2761 };
2762
2763 module_pci_driver(azx_driver);