include/uapi/linux/idxd.h

   1 /* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */
   2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
   3 #ifndef _USR_IDXD_H_
   4 #define _USR_IDXD_H_
   5
   6 #ifdef __KERNEL__
   7 #include <linux/types.h>
   8 #else
   9 #include <stdint.h>
  10 #endif
  11
  12 /* Descriptor flags */
  13 #define IDXD_OP_FLAG_FENCE      0x0001
  14 #define IDXD_OP_FLAG_BOF        0x0002
  15 #define IDXD_OP_FLAG_CRAV       0x0004
  16 #define IDXD_OP_FLAG_RCR        0x0008
  17 #define IDXD_OP_FLAG_RCI        0x0010
  18 #define IDXD_OP_FLAG_CRSTS      0x0020
  19 #define IDXD_OP_FLAG_CR         0x0080
  20 #define IDXD_OP_FLAG_CC         0x0100
  21 #define IDXD_OP_FLAG_ADDR1_TCS  0x0200
  22 #define IDXD_OP_FLAG_ADDR2_TCS  0x0400
  23 #define IDXD_OP_FLAG_ADDR3_TCS  0x0800
  24 #define IDXD_OP_FLAG_CR_TCS     0x1000
  25 #define IDXD_OP_FLAG_STORD      0x2000
  26 #define IDXD_OP_FLAG_DRDBK      0x4000
  27 #define IDXD_OP_FLAG_DSTS       0x8000
  28
  29 /* IAX */
  30 #define IDXD_OP_FLAG_RD_SRC2_AECS       0x010000
  31
  32 /* Opcode */
  33 enum dsa_opcode {
  34         DSA_OPCODE_NOOP = 0,
  35         DSA_OPCODE_BATCH,
  36         DSA_OPCODE_DRAIN,
  37         DSA_OPCODE_MEMMOVE,
  38         DSA_OPCODE_MEMFILL,
  39         DSA_OPCODE_COMPARE,
  40         DSA_OPCODE_COMPVAL,
  41         DSA_OPCODE_CR_DELTA,
  42         DSA_OPCODE_AP_DELTA,
  43         DSA_OPCODE_DUALCAST,
  44         DSA_OPCODE_CRCGEN = 0x10,
  45         DSA_OPCODE_COPY_CRC,
  46         DSA_OPCODE_DIF_CHECK,
  47         DSA_OPCODE_DIF_INS,
  48         DSA_OPCODE_DIF_STRP,
  49         DSA_OPCODE_DIF_UPDT,
  50         DSA_OPCODE_CFLUSH = 0x20,
  51 };
  52
  53 enum iax_opcode {
  54         IAX_OPCODE_NOOP = 0,
  55         IAX_OPCODE_DRAIN = 2,
  56         IAX_OPCODE_MEMMOVE,
  57         IAX_OPCODE_DECOMPRESS = 0x42,
  58         IAX_OPCODE_COMPRESS,
  59 };
  60
  61 /* Completion record status */
  62 enum dsa_completion_status {
  63         DSA_COMP_NONE = 0,
  64         DSA_COMP_SUCCESS,
  65         DSA_COMP_SUCCESS_PRED,
  66         DSA_COMP_PAGE_FAULT_NOBOF,
  67         DSA_COMP_PAGE_FAULT_IR,
  68         DSA_COMP_BATCH_FAIL,
  69         DSA_COMP_BATCH_PAGE_FAULT,
  70         DSA_COMP_DR_OFFSET_NOINC,
  71         DSA_COMP_DR_OFFSET_ERANGE,
  72         DSA_COMP_DIF_ERR,
  73         DSA_COMP_BAD_OPCODE = 0x10,
  74         DSA_COMP_INVALID_FLAGS,
  75         DSA_COMP_NOZERO_RESERVE,
  76         DSA_COMP_XFER_ERANGE,
  77         DSA_COMP_DESC_CNT_ERANGE,
  78         DSA_COMP_DR_ERANGE,
  79         DSA_COMP_OVERLAP_BUFFERS,
  80         DSA_COMP_DCAST_ERR,
  81         DSA_COMP_DESCLIST_ALIGN,
  82         DSA_COMP_INT_HANDLE_INVAL,
  83         DSA_COMP_CRA_XLAT,
  84         DSA_COMP_CRA_ALIGN,
  85         DSA_COMP_ADDR_ALIGN,
  86         DSA_COMP_PRIV_BAD,
  87         DSA_COMP_TRAFFIC_CLASS_CONF,
  88         DSA_COMP_PFAULT_RDBA,
  89         DSA_COMP_HW_ERR1,
  90         DSA_COMP_HW_ERR_DRB,
  91         DSA_COMP_TRANSLATION_FAIL,
  92 };
  93
  94 enum iax_completion_status {
  95         IAX_COMP_NONE = 0,
  96         IAX_COMP_SUCCESS,
  97         IAX_COMP_PAGE_FAULT_IR = 0x04,
  98         IAX_COMP_OUTBUF_OVERFLOW,
  99         IAX_COMP_BAD_OPCODE = 0x10,
 100         IAX_COMP_INVALID_FLAGS,
 101         IAX_COMP_NOZERO_RESERVE,
 102         IAX_COMP_INVALID_SIZE,
 103         IAX_COMP_OVERLAP_BUFFERS = 0x16,
 104         IAX_COMP_INT_HANDLE_INVAL = 0x19,
 105         IAX_COMP_CRA_XLAT,
 106         IAX_COMP_CRA_ALIGN,
 107         IAX_COMP_ADDR_ALIGN,
 108         IAX_COMP_PRIV_BAD,
 109         IAX_COMP_TRAFFIC_CLASS_CONF,
 110         IAX_COMP_PFAULT_RDBA,
 111         IAX_COMP_HW_ERR1,
 112         IAX_COMP_HW_ERR_DRB,
 113         IAX_COMP_TRANSLATION_FAIL,
 114         IAX_COMP_PRS_TIMEOUT,
 115         IAX_COMP_WATCHDOG,
 116         IAX_COMP_INVALID_COMP_FLAG = 0x30,
 117         IAX_COMP_INVALID_FILTER_FLAG,
 118         IAX_COMP_INVALID_NUM_ELEMS = 0x33,
 119 };
 120
 121 #define DSA_COMP_STATUS_MASK            0x7f
 122 #define DSA_COMP_STATUS_WRITE           0x80
 123
 124 struct dsa_hw_desc {
 125         uint32_t        pasid:20;
 126         uint32_t        rsvd:11;
 127         uint32_t        priv:1;
 128         uint32_t        flags:24;
 129         uint32_t        opcode:8;
 130         uint64_t        completion_addr;
 131         union {
 132                 uint64_t        src_addr;
 133                 uint64_t        rdback_addr;
 134                 uint64_t        pattern;
 135                 uint64_t        desc_list_addr;
 136         };
 137         union {
 138                 uint64_t        dst_addr;
 139                 uint64_t        rdback_addr2;
 140                 uint64_t        src2_addr;
 141                 uint64_t        comp_pattern;
 142         };
 143         union {
 144                 uint32_t        xfer_size;
 145                 uint32_t        desc_count;
 146         };
 147         uint16_t        int_handle;
 148         uint16_t        rsvd1;
 149         union {
 150                 uint8_t         expected_res;
 151                 /* create delta record */
 152                 struct {
 153                         uint64_t        delta_addr;
 154                         uint32_t        max_delta_size;
 155                         uint32_t        delt_rsvd;
 156                         uint8_t         expected_res_mask;
 157                 };
 158                 uint32_t        delta_rec_size;
 159                 uint64_t        dest2;
 160                 /* CRC */
 161                 struct {
 162                         uint32_t        crc_seed;
 163                         uint32_t        crc_rsvd;
 164                         uint64_t        seed_addr;
 165                 };
 166                 /* DIF check or strip */
 167                 struct {
 168                         uint8_t         src_dif_flags;
 169                         uint8_t         dif_chk_res;
 170                         uint8_t         dif_chk_flags;
 171                         uint8_t         dif_chk_res2[5];
 172                         uint32_t        chk_ref_tag_seed;
 173                         uint16_t        chk_app_tag_mask;
 174                         uint16_t        chk_app_tag_seed;
 175                 };
 176                 /* DIF insert */
 177                 struct {
 178                         uint8_t         dif_ins_res;
 179                         uint8_t         dest_dif_flag;
 180                         uint8_t         dif_ins_flags;
 181                         uint8_t         dif_ins_res2[13];
 182                         uint32_t        ins_ref_tag_seed;
 183                         uint16_t        ins_app_tag_mask;
 184                         uint16_t        ins_app_tag_seed;
 185                 };
 186                 /* DIF update */
 187                 struct {
 188                         uint8_t         src_upd_flags;
 189                         uint8_t         upd_dest_flags;
 190                         uint8_t         dif_upd_flags;
 191                         uint8_t         dif_upd_res[5];
 192                         uint32_t        src_ref_tag_seed;
 193                         uint16_t        src_app_tag_mask;
 194                         uint16_t        src_app_tag_seed;
 195                         uint32_t        dest_ref_tag_seed;
 196                         uint16_t        dest_app_tag_mask;
 197                         uint16_t        dest_app_tag_seed;
 198                 };
 199
 200                 uint8_t         op_specific[24];
 201         };
 202 } __attribute__((packed));
 203
 204 struct iax_hw_desc {
 205         uint32_t        pasid:20;
 206         uint32_t        rsvd:11;
 207         uint32_t        priv:1;
 208         uint32_t        flags:24;
 209         uint32_t        opcode:8;
 210         uint64_t        completion_addr;
 211         uint64_t        src1_addr;
 212         uint64_t        dst_addr;
 213         uint32_t        src1_size;
 214         uint16_t        int_handle;
 215         union {
 216                 uint16_t        compr_flags;
 217                 uint16_t        decompr_flags;
 218         };
 219         uint64_t        src2_addr;
 220         uint32_t        max_dst_size;
 221         uint32_t        src2_size;
 222         uint32_t        filter_flags;
 223         uint32_t        num_inputs;
 224 } __attribute__((packed));
 225
 226 struct dsa_raw_desc {
 227         uint64_t        field[8];
 228 } __attribute__((packed));
 229
 230 /*
 231  * The status field will be modified by hardware, therefore it should be
 232  * volatile and prevent the compiler from optimize the read.
 233  */
 234 struct dsa_completion_record {
 235         volatile uint8_t        status;
 236         union {
 237                 uint8_t         result;
 238                 uint8_t         dif_status;
 239         };
 240         uint16_t                rsvd;
 241         uint32_t                bytes_completed;
 242         uint64_t                fault_addr;
 243         union {
 244                 /* common record */
 245                 struct {
 246                         uint32_t        invalid_flags:24;
 247                         uint32_t        rsvd2:8;
 248                 };
 249
 250                 uint32_t        delta_rec_size;
 251                 uint32_t        crc_val;
 252
 253                 /* DIF check & strip */
 254                 struct {
 255                         uint32_t        dif_chk_ref_tag;
 256                         uint16_t        dif_chk_app_tag_mask;
 257                         uint16_t        dif_chk_app_tag;
 258                 };
 259
 260                 /* DIF insert */
 261                 struct {
 262                         uint64_t        dif_ins_res;
 263                         uint32_t        dif_ins_ref_tag;
 264                         uint16_t        dif_ins_app_tag_mask;
 265                         uint16_t        dif_ins_app_tag;
 266                 };
 267
 268                 /* DIF update */
 269                 struct {
 270                         uint32_t        dif_upd_src_ref_tag;
 271                         uint16_t        dif_upd_src_app_tag_mask;
 272                         uint16_t        dif_upd_src_app_tag;
 273                         uint32_t        dif_upd_dest_ref_tag;
 274                         uint16_t        dif_upd_dest_app_tag_mask;
 275                         uint16_t        dif_upd_dest_app_tag;
 276                 };
 277
 278                 uint8_t         op_specific[16];
 279         };
 280 } __attribute__((packed));
 281
 282 struct dsa_raw_completion_record {
 283         uint64_t        field[4];
 284 } __attribute__((packed));
 285
 286 struct iax_completion_record {
 287         volatile uint8_t        status;
 288         uint8_t                 error_code;
 289         uint16_t                rsvd;
 290         uint32_t                bytes_completed;
 291         uint64_t                fault_addr;
 292         uint32_t                invalid_flags;
 293         uint32_t                rsvd2;
 294         uint32_t                output_size;
 295         uint8_t                 output_bits;
 296         uint8_t                 rsvd3;
 297         uint16_t                rsvd4;
 298         uint64_t                rsvd5[4];
 299 } __attribute__((packed));
 300
 301 struct iax_raw_completion_record {
 302         uint64_t        field[8];
 303 } __attribute__((packed));
 304
 305 #endif