include/uapi/linux/idxd.h

   1 /* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */
   2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
   3 #ifndef _USR_IDXD_H_
   4 #define _USR_IDXD_H_
   5
   6 #ifdef __KERNEL__
   7 #include <linux/types.h>
   8 #else
   9 #include <stdint.h>
  10 #endif
  11
  12 /* Driver command error status */
  13 enum idxd_scmd_stat {
  14         IDXD_SCMD_DEV_ENABLED = 0x80000010,
  15         IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020,
  16         IDXD_SCMD_WQ_ENABLED = 0x80000021,
  17         IDXD_SCMD_DEV_DMA_ERR = 0x80020000,
  18         IDXD_SCMD_WQ_NO_GRP = 0x80030000,
  19         IDXD_SCMD_WQ_NO_NAME = 0x80040000,
  20         IDXD_SCMD_WQ_NO_SVM = 0x80050000,
  21         IDXD_SCMD_WQ_NO_THRESH = 0x80060000,
  22         IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000,
  23         IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000,
  24         IDXD_SCMD_PERCPU_ERR = 0x80090000,
  25         IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000,
  26         IDXD_SCMD_CDEV_ERR = 0x800b0000,
  27         IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000,
  28         IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000,
  29         IDXD_SCMD_WQ_NO_SIZE = 0x800e0000,
  30         IDXD_SCMD_WQ_NO_PRIV = 0x800f0000,
  31 };
  32
  33 #define IDXD_SCMD_SOFTERR_MASK  0x80000000
  34 #define IDXD_SCMD_SOFTERR_SHIFT 16
  35
  36 /* Descriptor flags */
  37 #define IDXD_OP_FLAG_FENCE      0x0001
  38 #define IDXD_OP_FLAG_BOF        0x0002
  39 #define IDXD_OP_FLAG_CRAV       0x0004
  40 #define IDXD_OP_FLAG_RCR        0x0008
  41 #define IDXD_OP_FLAG_RCI        0x0010
  42 #define IDXD_OP_FLAG_CRSTS      0x0020
  43 #define IDXD_OP_FLAG_CR         0x0080
  44 #define IDXD_OP_FLAG_CC         0x0100
  45 #define IDXD_OP_FLAG_ADDR1_TCS  0x0200
  46 #define IDXD_OP_FLAG_ADDR2_TCS  0x0400
  47 #define IDXD_OP_FLAG_ADDR3_TCS  0x0800
  48 #define IDXD_OP_FLAG_CR_TCS     0x1000
  49 #define IDXD_OP_FLAG_STORD      0x2000
  50 #define IDXD_OP_FLAG_DRDBK      0x4000
  51 #define IDXD_OP_FLAG_DSTS       0x8000
  52
  53 /* IAX */
  54 #define IDXD_OP_FLAG_RD_SRC2_AECS       0x010000
  55
  56 /* Opcode */
  57 enum dsa_opcode {
  58         DSA_OPCODE_NOOP = 0,
  59         DSA_OPCODE_BATCH,
  60         DSA_OPCODE_DRAIN,
  61         DSA_OPCODE_MEMMOVE,
  62         DSA_OPCODE_MEMFILL,
  63         DSA_OPCODE_COMPARE,
  64         DSA_OPCODE_COMPVAL,
  65         DSA_OPCODE_CR_DELTA,
  66         DSA_OPCODE_AP_DELTA,
  67         DSA_OPCODE_DUALCAST,
  68         DSA_OPCODE_CRCGEN = 0x10,
  69         DSA_OPCODE_COPY_CRC,
  70         DSA_OPCODE_DIF_CHECK,
  71         DSA_OPCODE_DIF_INS,
  72         DSA_OPCODE_DIF_STRP,
  73         DSA_OPCODE_DIF_UPDT,
  74         DSA_OPCODE_CFLUSH = 0x20,
  75 };
  76
  77 enum iax_opcode {
  78         IAX_OPCODE_NOOP = 0,
  79         IAX_OPCODE_DRAIN = 2,
  80         IAX_OPCODE_MEMMOVE,
  81         IAX_OPCODE_DECOMPRESS = 0x42,
  82         IAX_OPCODE_COMPRESS,
  83 };
  84
  85 /* Completion record status */
  86 enum dsa_completion_status {
  87         DSA_COMP_NONE = 0,
  88         DSA_COMP_SUCCESS,
  89         DSA_COMP_SUCCESS_PRED,
  90         DSA_COMP_PAGE_FAULT_NOBOF,
  91         DSA_COMP_PAGE_FAULT_IR,
  92         DSA_COMP_BATCH_FAIL,
  93         DSA_COMP_BATCH_PAGE_FAULT,
  94         DSA_COMP_DR_OFFSET_NOINC,
  95         DSA_COMP_DR_OFFSET_ERANGE,
  96         DSA_COMP_DIF_ERR,
  97         DSA_COMP_BAD_OPCODE = 0x10,
  98         DSA_COMP_INVALID_FLAGS,
  99         DSA_COMP_NOZERO_RESERVE,
 100         DSA_COMP_XFER_ERANGE,
 101         DSA_COMP_DESC_CNT_ERANGE,
 102         DSA_COMP_DR_ERANGE,
 103         DSA_COMP_OVERLAP_BUFFERS,
 104         DSA_COMP_DCAST_ERR,
 105         DSA_COMP_DESCLIST_ALIGN,
 106         DSA_COMP_INT_HANDLE_INVAL,
 107         DSA_COMP_CRA_XLAT,
 108         DSA_COMP_CRA_ALIGN,
 109         DSA_COMP_ADDR_ALIGN,
 110         DSA_COMP_PRIV_BAD,
 111         DSA_COMP_TRAFFIC_CLASS_CONF,
 112         DSA_COMP_PFAULT_RDBA,
 113         DSA_COMP_HW_ERR1,
 114         DSA_COMP_HW_ERR_DRB,
 115         DSA_COMP_TRANSLATION_FAIL,
 116 };
 117
 118 enum iax_completion_status {
 119         IAX_COMP_NONE = 0,
 120         IAX_COMP_SUCCESS,
 121         IAX_COMP_PAGE_FAULT_IR = 0x04,
 122         IAX_COMP_OUTBUF_OVERFLOW,
 123         IAX_COMP_BAD_OPCODE = 0x10,
 124         IAX_COMP_INVALID_FLAGS,
 125         IAX_COMP_NOZERO_RESERVE,
 126         IAX_COMP_INVALID_SIZE,
 127         IAX_COMP_OVERLAP_BUFFERS = 0x16,
 128         IAX_COMP_INT_HANDLE_INVAL = 0x19,
 129         IAX_COMP_CRA_XLAT,
 130         IAX_COMP_CRA_ALIGN,
 131         IAX_COMP_ADDR_ALIGN,
 132         IAX_COMP_PRIV_BAD,
 133         IAX_COMP_TRAFFIC_CLASS_CONF,
 134         IAX_COMP_PFAULT_RDBA,
 135         IAX_COMP_HW_ERR1,
 136         IAX_COMP_HW_ERR_DRB,
 137         IAX_COMP_TRANSLATION_FAIL,
 138         IAX_COMP_PRS_TIMEOUT,
 139         IAX_COMP_WATCHDOG,
 140         IAX_COMP_INVALID_COMP_FLAG = 0x30,
 141         IAX_COMP_INVALID_FILTER_FLAG,
 142         IAX_COMP_INVALID_NUM_ELEMS = 0x33,
 143 };
 144
 145 #define DSA_COMP_STATUS_MASK            0x7f
 146 #define DSA_COMP_STATUS_WRITE           0x80
 147
 148 struct dsa_hw_desc {
 149         uint32_t        pasid:20;
 150         uint32_t        rsvd:11;
 151         uint32_t        priv:1;
 152         uint32_t        flags:24;
 153         uint32_t        opcode:8;
 154         uint64_t        completion_addr;
 155         union {
 156                 uint64_t        src_addr;
 157                 uint64_t        rdback_addr;
 158                 uint64_t        pattern;
 159                 uint64_t        desc_list_addr;
 160         };
 161         union {
 162                 uint64_t        dst_addr;
 163                 uint64_t        rdback_addr2;
 164                 uint64_t        src2_addr;
 165                 uint64_t        comp_pattern;
 166         };
 167         union {
 168                 uint32_t        xfer_size;
 169                 uint32_t        desc_count;
 170         };
 171         uint16_t        int_handle;
 172         uint16_t        rsvd1;
 173         union {
 174                 uint8_t         expected_res;
 175                 /* create delta record */
 176                 struct {
 177                         uint64_t        delta_addr;
 178                         uint32_t        max_delta_size;
 179                         uint32_t        delt_rsvd;
 180                         uint8_t         expected_res_mask;
 181                 };
 182                 uint32_t        delta_rec_size;
 183                 uint64_t        dest2;
 184                 /* CRC */
 185                 struct {
 186                         uint32_t        crc_seed;
 187                         uint32_t        crc_rsvd;
 188                         uint64_t        seed_addr;
 189                 };
 190                 /* DIF check or strip */
 191                 struct {
 192                         uint8_t         src_dif_flags;
 193                         uint8_t         dif_chk_res;
 194                         uint8_t         dif_chk_flags;
 195                         uint8_t         dif_chk_res2[5];
 196                         uint32_t        chk_ref_tag_seed;
 197                         uint16_t        chk_app_tag_mask;
 198                         uint16_t        chk_app_tag_seed;
 199                 };
 200                 /* DIF insert */
 201                 struct {
 202                         uint8_t         dif_ins_res;
 203                         uint8_t         dest_dif_flag;
 204                         uint8_t         dif_ins_flags;
 205                         uint8_t         dif_ins_res2[13];
 206                         uint32_t        ins_ref_tag_seed;
 207                         uint16_t        ins_app_tag_mask;
 208                         uint16_t        ins_app_tag_seed;
 209                 };
 210                 /* DIF update */
 211                 struct {
 212                         uint8_t         src_upd_flags;
 213                         uint8_t         upd_dest_flags;
 214                         uint8_t         dif_upd_flags;
 215                         uint8_t         dif_upd_res[5];
 216                         uint32_t        src_ref_tag_seed;
 217                         uint16_t        src_app_tag_mask;
 218                         uint16_t        src_app_tag_seed;
 219                         uint32_t        dest_ref_tag_seed;
 220                         uint16_t        dest_app_tag_mask;
 221                         uint16_t        dest_app_tag_seed;
 222                 };
 223
 224                 uint8_t         op_specific[24];
 225         };
 226 } __attribute__((packed));
 227
 228 struct iax_hw_desc {
 229         uint32_t        pasid:20;
 230         uint32_t        rsvd:11;
 231         uint32_t        priv:1;
 232         uint32_t        flags:24;
 233         uint32_t        opcode:8;
 234         uint64_t        completion_addr;
 235         uint64_t        src1_addr;
 236         uint64_t        dst_addr;
 237         uint32_t        src1_size;
 238         uint16_t        int_handle;
 239         union {
 240                 uint16_t        compr_flags;
 241                 uint16_t        decompr_flags;
 242         };
 243         uint64_t        src2_addr;
 244         uint32_t        max_dst_size;
 245         uint32_t        src2_size;
 246         uint32_t        filter_flags;
 247         uint32_t        num_inputs;
 248 } __attribute__((packed));
 249
 250 struct dsa_raw_desc {
 251         uint64_t        field[8];
 252 } __attribute__((packed));
 253
 254 /*
 255  * The status field will be modified by hardware, therefore it should be
 256  * volatile and prevent the compiler from optimize the read.
 257  */
 258 struct dsa_completion_record {
 259         volatile uint8_t        status;
 260         union {
 261                 uint8_t         result;
 262                 uint8_t         dif_status;
 263         };
 264         uint16_t                rsvd;
 265         uint32_t                bytes_completed;
 266         uint64_t                fault_addr;
 267         union {
 268                 /* common record */
 269                 struct {
 270                         uint32_t        invalid_flags:24;
 271                         uint32_t        rsvd2:8;
 272                 };
 273
 274                 uint32_t        delta_rec_size;
 275                 uint32_t        crc_val;
 276
 277                 /* DIF check & strip */
 278                 struct {
 279                         uint32_t        dif_chk_ref_tag;
 280                         uint16_t        dif_chk_app_tag_mask;
 281                         uint16_t        dif_chk_app_tag;
 282                 };
 283
 284                 /* DIF insert */
 285                 struct {
 286                         uint64_t        dif_ins_res;
 287                         uint32_t        dif_ins_ref_tag;
 288                         uint16_t        dif_ins_app_tag_mask;
 289                         uint16_t        dif_ins_app_tag;
 290                 };
 291
 292                 /* DIF update */
 293                 struct {
 294                         uint32_t        dif_upd_src_ref_tag;
 295                         uint16_t        dif_upd_src_app_tag_mask;
 296                         uint16_t        dif_upd_src_app_tag;
 297                         uint32_t        dif_upd_dest_ref_tag;
 298                         uint16_t        dif_upd_dest_app_tag_mask;
 299                         uint16_t        dif_upd_dest_app_tag;
 300                 };
 301
 302                 uint8_t         op_specific[16];
 303         };
 304 } __attribute__((packed));
 305
 306 struct dsa_raw_completion_record {
 307         uint64_t        field[4];
 308 } __attribute__((packed));
 309
 310 struct iax_completion_record {
 311         volatile uint8_t        status;
 312         uint8_t                 error_code;
 313         uint16_t                rsvd;
 314         uint32_t                bytes_completed;
 315         uint64_t                fault_addr;
 316         uint32_t                invalid_flags;
 317         uint32_t                rsvd2;
 318         uint32_t                output_size;
 319         uint8_t                 output_bits;
 320         uint8_t                 rsvd3;
 321         uint16_t                rsvd4;
 322         uint64_t                rsvd5[4];
 323 } __attribute__((packed));
 324
 325 struct iax_raw_completion_record {
 326         uint64_t        field[8];
 327 } __attribute__((packed));
 328
 329 #endif