2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #ifndef _UAPI_I915_DRM_H_
28 #define _UAPI_I915_DRM_H_
32 #if defined(__cplusplus)
36 /* Please note that modifications to all structs defined here are
37 * subject to backwards-compatibility constraints.
41 * DOC: uevents generated by i915 on it's device node
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
44 * event from the gpu l3 cache. Additional information supplied is ROW,
45 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
46 * track of these events and if a specific cache-line seems to have a
47 * persistent error remap it with the l3 remapping tool supplied in
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
51 * hangcheck. The error detection event is a good indicator of when things
52 * began to go badly. The value supplied with the event is a 1 upon error
53 * detection, and a 0 upon reset completion, signifying no more error
54 * exists. NOTE: Disabling hangcheck or reset via module parameter will
55 * cause the related events to not be seen.
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
58 * GPU. The value supplied with the event is always 1. NOTE: Disable
59 * reset via module parameter will cause this event to not be seen.
61 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
62 #define I915_ERROR_UEVENT "ERROR"
63 #define I915_RESET_UEVENT "RESET"
66 * struct i915_user_extension - Base class for defining a chain of extensions
68 * Many interfaces need to grow over time. In most cases we can simply
69 * extend the struct and have userspace pass in more data. Another option,
70 * as demonstrated by Vulkan's approach to providing extensions for forward
71 * and backward compatibility, is to use a list of optional structs to
72 * provide those extra details.
74 * The key advantage to using an extension chain is that it allows us to
75 * redefine the interface more easily than an ever growing struct of
76 * increasing complexity, and for large parts of that interface to be
77 * entirely optional. The downside is more pointer chasing; chasing across
78 * the __user boundary with pointers encapsulated inside u64.
84 * struct i915_user_extension ext3 {
85 * .next_extension = 0, // end
88 * struct i915_user_extension ext2 {
89 * .next_extension = (uintptr_t)&ext3,
92 * struct i915_user_extension ext1 {
93 * .next_extension = (uintptr_t)&ext2,
97 * Typically the struct i915_user_extension would be embedded in some uAPI
98 * struct, and in this case we would feed it the head of the chain(i.e ext1),
99 * which would then apply all of the above extensions.
102 struct i915_user_extension {
106 * Pointer to the next struct i915_user_extension, or zero if the end.
108 __u64 next_extension;
110 * @name: Name of the extension.
112 * Note that the name here is just some integer.
114 * Also note that the name space for this is not global for the whole
115 * driver, but rather its scope/meaning is limited to the specific piece
116 * of uAPI which has embedded the struct i915_user_extension.
122 * All undefined bits must be zero.
128 * Reserved for future use; must be zero.
134 * MOCS indexes used for GPU surfaces, defining the cacheability of the
135 * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
137 enum i915_mocs_table_index {
139 * Not cached anywhere, coherency between CPU and GPU accesses is
144 * Cacheability and coherency controlled by the kernel automatically
145 * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
146 * usage of the surface (used for display scanout or not).
150 * Cached in all GPU caches available on the platform.
151 * Coherency between CPU and GPU accesses to the surface is not
152 * guaranteed without extra synchronization.
158 * Different engines serve different roles, and there may be more than one
159 * engine serving each role. enum drm_i915_gem_engine_class provides a
160 * classification of the role of the engine, which may be used when requesting
161 * operations to be performed on a certain subset of engines, or for providing
162 * information about that group.
164 enum drm_i915_gem_engine_class {
165 I915_ENGINE_CLASS_RENDER = 0,
166 I915_ENGINE_CLASS_COPY = 1,
167 I915_ENGINE_CLASS_VIDEO = 2,
168 I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
170 /* should be kept compact */
172 I915_ENGINE_CLASS_INVALID = -1
176 * There may be more than one engine fulfilling any role within the system.
177 * Each engine of a class is given a unique instance number and therefore
178 * any engine can be specified by its class:instance tuplet. APIs that allow
179 * access to any engine in the system will use struct i915_engine_class_instance
180 * for this identification.
182 struct i915_engine_class_instance {
183 __u16 engine_class; /* see enum drm_i915_gem_engine_class */
184 __u16 engine_instance;
185 #define I915_ENGINE_CLASS_INVALID_NONE -1
186 #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
190 * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
194 enum drm_i915_pmu_engine_sample {
195 I915_SAMPLE_BUSY = 0,
196 I915_SAMPLE_WAIT = 1,
200 #define I915_PMU_SAMPLE_BITS (4)
201 #define I915_PMU_SAMPLE_MASK (0xf)
202 #define I915_PMU_SAMPLE_INSTANCE_BITS (8)
203 #define I915_PMU_CLASS_SHIFT \
204 (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
206 #define __I915_PMU_ENGINE(class, instance, sample) \
207 ((class) << I915_PMU_CLASS_SHIFT | \
208 (instance) << I915_PMU_SAMPLE_BITS | \
211 #define I915_PMU_ENGINE_BUSY(class, instance) \
212 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
214 #define I915_PMU_ENGINE_WAIT(class, instance) \
215 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
217 #define I915_PMU_ENGINE_SEMA(class, instance) \
218 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
220 #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
222 #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)
223 #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)
224 #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)
225 #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
226 #define I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4)
228 #define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY
230 /* Each region is a minimum of 16k, and there are at most 255 of them.
232 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
233 * of chars for next/prev indices */
234 #define I915_LOG_MIN_TEX_REGION_SIZE 14
236 typedef struct _drm_i915_init {
238 I915_INIT_DMA = 0x01,
239 I915_CLEANUP_DMA = 0x02,
240 I915_RESUME_DMA = 0x03
242 unsigned int mmio_offset;
243 int sarea_priv_offset;
244 unsigned int ring_start;
245 unsigned int ring_end;
246 unsigned int ring_size;
247 unsigned int front_offset;
248 unsigned int back_offset;
249 unsigned int depth_offset;
253 unsigned int pitch_bits;
254 unsigned int back_pitch;
255 unsigned int depth_pitch;
257 unsigned int chipset;
260 typedef struct _drm_i915_sarea {
261 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
262 int last_upload; /* last time texture was uploaded */
263 int last_enqueue; /* last time a buffer was enqueued */
264 int last_dispatch; /* age of the most recently dispatched buffer */
265 int ctxOwner; /* last context to upload state */
267 int pf_enabled; /* is pageflipping allowed? */
269 int pf_current_page; /* which buffer is being displayed? */
270 int perf_boxes; /* performance boxes to be displayed */
271 int width, height; /* screen size in pixels */
273 drm_handle_t front_handle;
277 drm_handle_t back_handle;
281 drm_handle_t depth_handle;
285 drm_handle_t tex_handle;
288 int log_tex_granularity;
290 int rotation; /* 0, 90, 180 or 270 */
294 int virtualX, virtualY;
296 unsigned int front_tiled;
297 unsigned int back_tiled;
298 unsigned int depth_tiled;
299 unsigned int rotated_tiled;
300 unsigned int rotated2_tiled;
311 /* fill out some space for old userspace triple buffer */
312 drm_handle_t unused_handle;
313 __u32 unused1, unused2, unused3;
315 /* buffer object handles for static buffers. May change
316 * over the lifetime of the client.
318 __u32 front_bo_handle;
319 __u32 back_bo_handle;
320 __u32 unused_bo_handle;
321 __u32 depth_bo_handle;
325 /* due to userspace building against these headers we need some compat here */
326 #define planeA_x pipeA_x
327 #define planeA_y pipeA_y
328 #define planeA_w pipeA_w
329 #define planeA_h pipeA_h
330 #define planeB_x pipeB_x
331 #define planeB_y pipeB_y
332 #define planeB_w pipeB_w
333 #define planeB_h pipeB_h
335 /* Flags for perf_boxes
337 #define I915_BOX_RING_EMPTY 0x1
338 #define I915_BOX_FLIP 0x2
339 #define I915_BOX_WAIT 0x4
340 #define I915_BOX_TEXTURE_LOAD 0x8
341 #define I915_BOX_LOST_CONTEXT 0x10
344 * i915 specific ioctls.
346 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
347 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
348 * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
350 #define DRM_I915_INIT 0x00
351 #define DRM_I915_FLUSH 0x01
352 #define DRM_I915_FLIP 0x02
353 #define DRM_I915_BATCHBUFFER 0x03
354 #define DRM_I915_IRQ_EMIT 0x04
355 #define DRM_I915_IRQ_WAIT 0x05
356 #define DRM_I915_GETPARAM 0x06
357 #define DRM_I915_SETPARAM 0x07
358 #define DRM_I915_ALLOC 0x08
359 #define DRM_I915_FREE 0x09
360 #define DRM_I915_INIT_HEAP 0x0a
361 #define DRM_I915_CMDBUFFER 0x0b
362 #define DRM_I915_DESTROY_HEAP 0x0c
363 #define DRM_I915_SET_VBLANK_PIPE 0x0d
364 #define DRM_I915_GET_VBLANK_PIPE 0x0e
365 #define DRM_I915_VBLANK_SWAP 0x0f
366 #define DRM_I915_HWS_ADDR 0x11
367 #define DRM_I915_GEM_INIT 0x13
368 #define DRM_I915_GEM_EXECBUFFER 0x14
369 #define DRM_I915_GEM_PIN 0x15
370 #define DRM_I915_GEM_UNPIN 0x16
371 #define DRM_I915_GEM_BUSY 0x17
372 #define DRM_I915_GEM_THROTTLE 0x18
373 #define DRM_I915_GEM_ENTERVT 0x19
374 #define DRM_I915_GEM_LEAVEVT 0x1a
375 #define DRM_I915_GEM_CREATE 0x1b
376 #define DRM_I915_GEM_PREAD 0x1c
377 #define DRM_I915_GEM_PWRITE 0x1d
378 #define DRM_I915_GEM_MMAP 0x1e
379 #define DRM_I915_GEM_SET_DOMAIN 0x1f
380 #define DRM_I915_GEM_SW_FINISH 0x20
381 #define DRM_I915_GEM_SET_TILING 0x21
382 #define DRM_I915_GEM_GET_TILING 0x22
383 #define DRM_I915_GEM_GET_APERTURE 0x23
384 #define DRM_I915_GEM_MMAP_GTT 0x24
385 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
386 #define DRM_I915_GEM_MADVISE 0x26
387 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27
388 #define DRM_I915_OVERLAY_ATTRS 0x28
389 #define DRM_I915_GEM_EXECBUFFER2 0x29
390 #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
391 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a
392 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b
393 #define DRM_I915_GEM_WAIT 0x2c
394 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d
395 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
396 #define DRM_I915_GEM_SET_CACHING 0x2f
397 #define DRM_I915_GEM_GET_CACHING 0x30
398 #define DRM_I915_REG_READ 0x31
399 #define DRM_I915_GET_RESET_STATS 0x32
400 #define DRM_I915_GEM_USERPTR 0x33
401 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
402 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
403 #define DRM_I915_PERF_OPEN 0x36
404 #define DRM_I915_PERF_ADD_CONFIG 0x37
405 #define DRM_I915_PERF_REMOVE_CONFIG 0x38
406 #define DRM_I915_QUERY 0x39
407 #define DRM_I915_GEM_VM_CREATE 0x3a
408 #define DRM_I915_GEM_VM_DESTROY 0x3b
409 #define DRM_I915_GEM_CREATE_EXT 0x3c
410 /* Must be kept compact -- no holes */
412 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
413 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
414 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
415 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
416 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
417 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
418 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
419 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
420 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
421 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
422 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
423 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
424 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
425 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
426 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
427 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
428 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
429 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
430 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
431 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
432 #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
433 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
434 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
435 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
436 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
437 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
438 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
439 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
440 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
441 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
442 #define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext)
443 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
444 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
445 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
446 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
447 #define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset)
448 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
449 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
450 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
451 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
452 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
453 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
454 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
455 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
456 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
457 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
458 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
459 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
460 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
461 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
462 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
463 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
464 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
465 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
466 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
467 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
468 #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
469 #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
470 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
471 #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
472 #define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
473 #define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
475 /* Allow drivers to submit batchbuffers directly to hardware, relying
476 * on the security mechanisms provided by hardware.
478 typedef struct drm_i915_batchbuffer {
479 int start; /* agp offset */
480 int used; /* nr bytes in use */
481 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
482 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
483 int num_cliprects; /* mulitpass with multiple cliprects? */
484 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
485 } drm_i915_batchbuffer_t;
487 /* As above, but pass a pointer to userspace buffer which can be
488 * validated by the kernel prior to sending to hardware.
490 typedef struct _drm_i915_cmdbuffer {
491 char __user *buf; /* pointer to userspace command buffer */
492 int sz; /* nr bytes in buf */
493 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
494 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
495 int num_cliprects; /* mulitpass with multiple cliprects? */
496 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
497 } drm_i915_cmdbuffer_t;
499 /* Userspace can request & wait on irq's:
501 typedef struct drm_i915_irq_emit {
503 } drm_i915_irq_emit_t;
505 typedef struct drm_i915_irq_wait {
507 } drm_i915_irq_wait_t;
510 * Different modes of per-process Graphics Translation Table,
511 * see I915_PARAM_HAS_ALIASING_PPGTT
513 #define I915_GEM_PPGTT_NONE 0
514 #define I915_GEM_PPGTT_ALIASING 1
515 #define I915_GEM_PPGTT_FULL 2
517 /* Ioctl to query kernel params:
519 #define I915_PARAM_IRQ_ACTIVE 1
520 #define I915_PARAM_ALLOW_BATCHBUFFER 2
521 #define I915_PARAM_LAST_DISPATCH 3
522 #define I915_PARAM_CHIPSET_ID 4
523 #define I915_PARAM_HAS_GEM 5
524 #define I915_PARAM_NUM_FENCES_AVAIL 6
525 #define I915_PARAM_HAS_OVERLAY 7
526 #define I915_PARAM_HAS_PAGEFLIPPING 8
527 #define I915_PARAM_HAS_EXECBUF2 9
528 #define I915_PARAM_HAS_BSD 10
529 #define I915_PARAM_HAS_BLT 11
530 #define I915_PARAM_HAS_RELAXED_FENCING 12
531 #define I915_PARAM_HAS_COHERENT_RINGS 13
532 #define I915_PARAM_HAS_EXEC_CONSTANTS 14
533 #define I915_PARAM_HAS_RELAXED_DELTA 15
534 #define I915_PARAM_HAS_GEN7_SOL_RESET 16
535 #define I915_PARAM_HAS_LLC 17
536 #define I915_PARAM_HAS_ALIASING_PPGTT 18
537 #define I915_PARAM_HAS_WAIT_TIMEOUT 19
538 #define I915_PARAM_HAS_SEMAPHORES 20
539 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
540 #define I915_PARAM_HAS_VEBOX 22
541 #define I915_PARAM_HAS_SECURE_BATCHES 23
542 #define I915_PARAM_HAS_PINNED_BATCHES 24
543 #define I915_PARAM_HAS_EXEC_NO_RELOC 25
544 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
545 #define I915_PARAM_HAS_WT 27
546 #define I915_PARAM_CMD_PARSER_VERSION 28
547 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
548 #define I915_PARAM_MMAP_VERSION 30
549 #define I915_PARAM_HAS_BSD2 31
550 #define I915_PARAM_REVISION 32
551 #define I915_PARAM_SUBSLICE_TOTAL 33
552 #define I915_PARAM_EU_TOTAL 34
553 #define I915_PARAM_HAS_GPU_RESET 35
554 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
555 #define I915_PARAM_HAS_EXEC_SOFTPIN 37
556 #define I915_PARAM_HAS_POOLED_EU 38
557 #define I915_PARAM_MIN_EU_IN_POOL 39
558 #define I915_PARAM_MMAP_GTT_VERSION 40
561 * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
562 * priorities and the driver will attempt to execute batches in priority order.
563 * The param returns a capability bitmask, nonzero implies that the scheduler
564 * is enabled, with different features present according to the mask.
566 * The initial priority for each batch is supplied by the context and is
567 * controlled via I915_CONTEXT_PARAM_PRIORITY.
569 #define I915_PARAM_HAS_SCHEDULER 41
570 #define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
571 #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
572 #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
573 #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
574 #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
576 * Indicates the 2k user priority levels are statically mapped into 3 buckets as
579 * -1k to -1 Low priority
581 * 1 to 1k Highest priority
583 #define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5)
585 #define I915_PARAM_HUC_STATUS 42
587 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
588 * synchronisation with implicit fencing on individual objects.
589 * See EXEC_OBJECT_ASYNC.
591 #define I915_PARAM_HAS_EXEC_ASYNC 43
593 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
594 * both being able to pass in a sync_file fd to wait upon before executing,
595 * and being able to return a new sync_file fd that is signaled when the
596 * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
598 #define I915_PARAM_HAS_EXEC_FENCE 44
600 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture
601 * user specified bufffers for post-mortem debugging of GPU hangs. See
602 * EXEC_OBJECT_CAPTURE.
604 #define I915_PARAM_HAS_EXEC_CAPTURE 45
606 #define I915_PARAM_SLICE_MASK 46
608 /* Assuming it's uniform for each slice, this queries the mask of subslices
609 * per-slice for this system.
611 #define I915_PARAM_SUBSLICE_MASK 47
614 * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer
615 * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST.
617 #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48
619 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
620 * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY.
622 #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49
625 * Query whether every context (both per-file default and user created) is
626 * isolated (insofar as HW supports). If this parameter is not true, then
627 * freshly created contexts may inherit values from an existing context,
628 * rather than default HW values. If true, it also ensures (insofar as HW
629 * supports) that all state set by this context will not leak to any other
632 * As not every engine across every gen support contexts, the returned
633 * value reports the support of context isolation for individual engines by
634 * returning a bitmask of each engine class set to true if that class supports
637 #define I915_PARAM_HAS_CONTEXT_ISOLATION 50
639 /* Frequency of the command streamer timestamps given by the *_TIMESTAMP
640 * registers. This used to be fixed per platform but from CNL onwards, this
641 * might vary depending on the parts.
643 #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
646 * Once upon a time we supposed that writes through the GGTT would be
647 * immediately in physical memory (once flushed out of the CPU path). However,
648 * on a few different processors and chipsets, this is not necessarily the case
649 * as the writes appear to be buffered internally. Thus a read of the backing
650 * storage (physical memory) via a different path (with different physical tags
651 * to the indirect write via the GGTT) will see stale values from before
652 * the GGTT write. Inside the kernel, we can for the most part keep track of
653 * the different read/write domains in use (e.g. set-domain), but the assumption
654 * of coherency is baked into the ABI, hence reporting its true state in this
657 * Reports true when writes via mmap_gtt are immediately visible following an
658 * lfence to flush the WCB.
660 * Reports false when writes via mmap_gtt are indeterminately delayed in an in
661 * internal buffer and are _not_ immediately visible to third parties accessing
662 * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC
663 * communications channel when reporting false is strongly disadvised.
665 #define I915_PARAM_MMAP_GTT_COHERENT 52
668 * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
669 * execution through use of explicit fence support.
670 * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
672 #define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
675 * Revision of the i915-perf uAPI. The value returned helps determine what
676 * i915-perf features are available. See drm_i915_perf_property_id.
678 #define I915_PARAM_PERF_REVISION 54
680 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
681 * timeline syncobj through drm_i915_gem_execbuffer_ext_timeline_fences. See
682 * I915_EXEC_USE_EXTENSIONS.
684 #define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
686 /* Query if the kernel supports the I915_USERPTR_PROBE flag. */
687 #define I915_PARAM_HAS_USERPTR_PROBE 56
689 /* Must be kept compact -- no holes and well documented */
691 typedef struct drm_i915_getparam {
694 * WARNING: Using pointers instead of fixed-size u64 means we need to write
695 * compat32 code. Don't repeat this mistake.
698 } drm_i915_getparam_t;
700 /* Ioctl to set kernel params:
702 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
703 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
704 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
705 #define I915_SETPARAM_NUM_USED_FENCES 4
706 /* Must be kept compact -- no holes */
708 typedef struct drm_i915_setparam {
711 } drm_i915_setparam_t;
713 /* A memory manager for regions of shared memory:
715 #define I915_MEM_REGION_AGP 1
717 typedef struct drm_i915_mem_alloc {
721 int __user *region_offset; /* offset from start of fb or agp */
722 } drm_i915_mem_alloc_t;
724 typedef struct drm_i915_mem_free {
727 } drm_i915_mem_free_t;
729 typedef struct drm_i915_mem_init_heap {
733 } drm_i915_mem_init_heap_t;
735 /* Allow memory manager to be torn down and re-initialized (eg on
738 typedef struct drm_i915_mem_destroy_heap {
740 } drm_i915_mem_destroy_heap_t;
742 /* Allow X server to configure which pipes to monitor for vblank signals
744 #define DRM_I915_VBLANK_PIPE_A 1
745 #define DRM_I915_VBLANK_PIPE_B 2
747 typedef struct drm_i915_vblank_pipe {
749 } drm_i915_vblank_pipe_t;
751 /* Schedule buffer swap at given vertical blank:
753 typedef struct drm_i915_vblank_swap {
754 drm_drawable_t drawable;
755 enum drm_vblank_seq_type seqtype;
756 unsigned int sequence;
757 } drm_i915_vblank_swap_t;
759 typedef struct drm_i915_hws_addr {
761 } drm_i915_hws_addr_t;
763 struct drm_i915_gem_init {
765 * Beginning offset in the GTT to be managed by the DRM memory
770 * Ending offset in the GTT to be managed by the DRM memory
776 struct drm_i915_gem_create {
778 * Requested size for the object.
780 * The (page-aligned) allocated size for the object will be returned.
784 * Returned handle for the object.
786 * Object handles are nonzero.
792 struct drm_i915_gem_pread {
793 /** Handle for the object being read. */
796 /** Offset into the object to read from */
798 /** Length of data to read */
801 * Pointer to write the data into.
803 * This is a fixed-size type for 32/64 compatibility.
808 struct drm_i915_gem_pwrite {
809 /** Handle for the object being written to. */
812 /** Offset into the object to write to */
814 /** Length of data to write */
817 * Pointer to read the data from.
819 * This is a fixed-size type for 32/64 compatibility.
824 struct drm_i915_gem_mmap {
825 /** Handle for the object being mapped. */
828 /** Offset in the object to map. */
831 * Length of data to map.
833 * The value will be page-aligned.
837 * Returned pointer the data was mapped at.
839 * This is a fixed-size type for 32/64 compatibility.
844 * Flags for extended behaviour.
846 * Added in version 2.
849 #define I915_MMAP_WC 0x1
852 struct drm_i915_gem_mmap_gtt {
853 /** Handle for the object being mapped. */
857 * Fake offset to use for subsequent mmap call
859 * This is a fixed-size type for 32/64 compatibility.
865 * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
867 * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
868 * and is used to retrieve the fake offset to mmap an object specified by &handle.
870 * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
871 * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
872 * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
874 struct drm_i915_gem_mmap_offset {
875 /** @handle: Handle for the object being mapped. */
877 /** @pad: Must be zero */
880 * @offset: The fake offset to use for subsequent mmap call
882 * This is a fixed-size type for 32/64 compatibility.
887 * @flags: Flags for extended behaviour.
889 * It is mandatory that one of the `MMAP_OFFSET` types
890 * should be included:
892 * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined)
893 * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
894 * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
895 * - `I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching.
897 * On devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid
898 * type. On devices without local memory, this caching mode is invalid.
900 * As caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will
901 * be used, depending on the object placement on creation. WB will be used
902 * when the object can only exist in system memory, WC otherwise.
906 #define I915_MMAP_OFFSET_GTT 0
907 #define I915_MMAP_OFFSET_WC 1
908 #define I915_MMAP_OFFSET_WB 2
909 #define I915_MMAP_OFFSET_UC 3
910 #define I915_MMAP_OFFSET_FIXED 4
913 * @extensions: Zero-terminated chain of extensions.
915 * No current extensions defined; mbz.
921 * struct drm_i915_gem_set_domain - Adjust the objects write or read domain, in
922 * preparation for accessing the pages via some CPU domain.
924 * Specifying a new write or read domain will flush the object out of the
925 * previous domain(if required), before then updating the objects domain
926 * tracking with the new domain.
928 * Note this might involve waiting for the object first if it is still active on
931 * Supported values for @read_domains and @write_domain:
933 * - I915_GEM_DOMAIN_WC: Uncached write-combined domain
934 * - I915_GEM_DOMAIN_CPU: CPU cache domain
935 * - I915_GEM_DOMAIN_GTT: Mappable aperture domain
937 * All other domains are rejected.
939 * Note that for discrete, starting from DG1, this is no longer supported, and
940 * is instead rejected. On such platforms the CPU domain is effectively static,
941 * where we also only support a single &drm_i915_gem_mmap_offset cache mode,
942 * which can't be set explicitly and instead depends on the object placements,
945 * Implicit caching rules, starting from DG1:
947 * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions)
948 * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and
949 * mapped as write-combined only.
951 * - Everything else is always allocated and mapped as write-back, with the
952 * guarantee that everything is also coherent with the GPU.
954 * Note that this is likely to change in the future again, where we might need
955 * more flexibility on future devices, so making this all explicit as part of a
956 * new &drm_i915_gem_create_ext extension is probable.
958 struct drm_i915_gem_set_domain {
959 /** @handle: Handle for the object. */
962 /** @read_domains: New read domains. */
966 * @write_domain: New write domain.
968 * Note that having something in the write domain implies it's in the
969 * read domain, and only that read domain.
974 struct drm_i915_gem_sw_finish {
975 /** Handle for the object */
979 struct drm_i915_gem_relocation_entry {
981 * Handle of the buffer being pointed to by this relocation entry.
983 * It's appealing to make this be an index into the mm_validate_entry
984 * list to refer to the buffer, but this allows the driver to create
985 * a relocation list for state buffers and not re-write it per
986 * exec using the buffer.
991 * Value to be added to the offset of the target buffer to make up
992 * the relocation entry.
996 /** Offset in the buffer the relocation entry will be written into */
1000 * Offset value of the target buffer that the relocation entry was last
1003 * If the buffer has the same offset as last time, we can skip syncing
1004 * and writing the relocation. This value is written back out by
1005 * the execbuffer ioctl when the relocation is written.
1007 __u64 presumed_offset;
1010 * Target memory domains read by this operation.
1015 * Target memory domains written by this operation.
1017 * Note that only one domain may be written by the whole
1018 * execbuffer operation, so that where there are conflicts,
1019 * the application will get -EINVAL back.
1025 * Intel memory domains
1027 * Most of these just align with the various caches in
1028 * the system and are used to flush and invalidate as
1029 * objects end up cached in different domains.
1032 #define I915_GEM_DOMAIN_CPU 0x00000001
1033 /** Render cache, used by 2D and 3D drawing */
1034 #define I915_GEM_DOMAIN_RENDER 0x00000002
1035 /** Sampler cache, used by texture engine */
1036 #define I915_GEM_DOMAIN_SAMPLER 0x00000004
1037 /** Command queue, used to load batch buffers */
1038 #define I915_GEM_DOMAIN_COMMAND 0x00000008
1039 /** Instruction cache, used by shader programs */
1040 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
1041 /** Vertex address cache */
1042 #define I915_GEM_DOMAIN_VERTEX 0x00000020
1043 /** GTT domain - aperture and scanout */
1044 #define I915_GEM_DOMAIN_GTT 0x00000040
1045 /** WC domain - uncached access */
1046 #define I915_GEM_DOMAIN_WC 0x00000080
1049 struct drm_i915_gem_exec_object {
1051 * User's handle for a buffer to be bound into the GTT for this
1056 /** Number of relocations to be performed on this buffer */
1057 __u32 relocation_count;
1059 * Pointer to array of struct drm_i915_gem_relocation_entry containing
1060 * the relocations to be performed in this buffer.
1064 /** Required alignment in graphics aperture */
1068 * Returned value of the updated offset of the object, for future
1069 * presumed_offset writes.
1074 /* DRM_IOCTL_I915_GEM_EXECBUFFER was removed in Linux 5.13 */
1075 struct drm_i915_gem_execbuffer {
1077 * List of buffers to be validated with their relocations to be
1078 * performend on them.
1080 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
1082 * These buffers must be listed in an order such that all relocations
1083 * a buffer is performing refer to buffers that have already appeared
1084 * in the validate list.
1089 /** Offset in the batchbuffer to start execution from. */
1090 __u32 batch_start_offset;
1091 /** Bytes used in batchbuffer from batch_start_offset */
1095 __u32 num_cliprects;
1096 /** This is a struct drm_clip_rect *cliprects */
1097 __u64 cliprects_ptr;
1100 struct drm_i915_gem_exec_object2 {
1102 * User's handle for a buffer to be bound into the GTT for this
1107 /** Number of relocations to be performed on this buffer */
1108 __u32 relocation_count;
1110 * Pointer to array of struct drm_i915_gem_relocation_entry containing
1111 * the relocations to be performed in this buffer.
1115 /** Required alignment in graphics aperture */
1119 * When the EXEC_OBJECT_PINNED flag is specified this is populated by
1120 * the user with the GTT offset at which this object will be pinned.
1121 * When the I915_EXEC_NO_RELOC flag is specified this must contain the
1122 * presumed_offset of the object.
1123 * During execbuffer2 the kernel populates it with the value of the
1124 * current GTT offset of the object, for future presumed_offset writes.
1128 #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
1129 #define EXEC_OBJECT_NEEDS_GTT (1<<1)
1130 #define EXEC_OBJECT_WRITE (1<<2)
1131 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
1132 #define EXEC_OBJECT_PINNED (1<<4)
1133 #define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
1134 /* The kernel implicitly tracks GPU activity on all GEM objects, and
1135 * synchronises operations with outstanding rendering. This includes
1136 * rendering on other devices if exported via dma-buf. However, sometimes
1137 * this tracking is too coarse and the user knows better. For example,
1138 * if the object is split into non-overlapping ranges shared between different
1139 * clients or engines (i.e. suballocating objects), the implicit tracking
1140 * by kernel assumes that each operation affects the whole object rather
1141 * than an individual range, causing needless synchronisation between clients.
1142 * The kernel will also forgo any CPU cache flushes prior to rendering from
1143 * the object as the client is expected to be also handling such domain
1146 * The kernel maintains the implicit tracking in order to manage resources
1147 * used by the GPU - this flag only disables the synchronisation prior to
1148 * rendering with this object in this execbuf.
1150 * Opting out of implicit synhronisation requires the user to do its own
1151 * explicit tracking to avoid rendering corruption. See, for example,
1152 * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
1154 #define EXEC_OBJECT_ASYNC (1<<6)
1155 /* Request that the contents of this execobject be copied into the error
1156 * state upon a GPU hang involving this batch for post-mortem debugging.
1157 * These buffers are recorded in no particular order as "user" in
1158 * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see
1159 * if the kernel supports this flag.
1161 #define EXEC_OBJECT_CAPTURE (1<<7)
1162 /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
1163 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)
1173 struct drm_i915_gem_exec_fence {
1175 * User's handle for a drm_syncobj to wait on or signal.
1179 #define I915_EXEC_FENCE_WAIT (1<<0)
1180 #define I915_EXEC_FENCE_SIGNAL (1<<1)
1181 #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
1186 * See drm_i915_gem_execbuffer_ext_timeline_fences.
1188 #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0
1191 * This structure describes an array of drm_syncobj and associated points for
1192 * timeline variants of drm_syncobj. It is invalid to append this structure to
1193 * the execbuf if I915_EXEC_FENCE_ARRAY is set.
1195 struct drm_i915_gem_execbuffer_ext_timeline_fences {
1196 struct i915_user_extension base;
1199 * Number of element in the handles_ptr & value_ptr arrays.
1204 * Pointer to an array of struct drm_i915_gem_exec_fence of length
1210 * Pointer to an array of u64 values of length fence_count. Values
1211 * must be 0 for a binary drm_syncobj. A Value of 0 for a timeline
1212 * drm_syncobj is invalid as it turns a drm_syncobj into a binary one.
1217 struct drm_i915_gem_execbuffer2 {
1219 * List of gem_exec_object2 structs
1224 /** Offset in the batchbuffer to start execution from. */
1225 __u32 batch_start_offset;
1226 /** Bytes used in batchbuffer from batch_start_offset */
1230 __u32 num_cliprects;
1232 * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
1233 * & I915_EXEC_USE_EXTENSIONS are not set.
1235 * If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array
1236 * of struct drm_i915_gem_exec_fence and num_cliprects is the length
1239 * If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a
1240 * single struct i915_user_extension and num_cliprects is 0.
1242 __u64 cliprects_ptr;
1243 #define I915_EXEC_RING_MASK (0x3f)
1244 #define I915_EXEC_DEFAULT (0<<0)
1245 #define I915_EXEC_RENDER (1<<0)
1246 #define I915_EXEC_BSD (2<<0)
1247 #define I915_EXEC_BLT (3<<0)
1248 #define I915_EXEC_VEBOX (4<<0)
1250 /* Used for switching the constants addressing mode on gen4+ RENDER ring.
1251 * Gen6+ only supports relative addressing to dynamic state (default) and
1252 * absolute addressing.
1254 * These flags are ignored for the BSD and BLT rings.
1256 #define I915_EXEC_CONSTANTS_MASK (3<<6)
1257 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
1258 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
1259 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
1261 __u64 rsvd1; /* now used for context info */
1265 /** Resets the SO write offset registers for transform feedback on gen7. */
1266 #define I915_EXEC_GEN7_SOL_RESET (1<<8)
1268 /** Request a privileged ("secure") batch buffer. Note only available for
1269 * DRM_ROOT_ONLY | DRM_MASTER processes.
1271 #define I915_EXEC_SECURE (1<<9)
1273 /** Inform the kernel that the batch is and will always be pinned. This
1274 * negates the requirement for a workaround to be performed to avoid
1275 * an incoherent CS (such as can be found on 830/845). If this flag is
1276 * not passed, the kernel will endeavour to make sure the batch is
1277 * coherent with the CS before execution. If this flag is passed,
1278 * userspace assumes the responsibility for ensuring the same.
1280 #define I915_EXEC_IS_PINNED (1<<10)
1282 /** Provide a hint to the kernel that the command stream and auxiliary
1283 * state buffers already holds the correct presumed addresses and so the
1284 * relocation process may be skipped if no buffers need to be moved in
1285 * preparation for the execbuffer.
1287 #define I915_EXEC_NO_RELOC (1<<11)
1289 /** Use the reloc.handle as an index into the exec object array rather
1290 * than as the per-file handle.
1292 #define I915_EXEC_HANDLE_LUT (1<<12)
1294 /** Used for switching BSD rings on the platforms with two BSD rings */
1295 #define I915_EXEC_BSD_SHIFT (13)
1296 #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)
1297 /* default ping-pong mode */
1298 #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)
1299 #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)
1300 #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)
1302 /** Tell the kernel that the batchbuffer is processed by
1303 * the resource streamer.
1305 #define I915_EXEC_RESOURCE_STREAMER (1<<15)
1307 /* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
1308 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1311 * Returns -EINVAL if the sync_file fd cannot be found.
1313 #define I915_EXEC_FENCE_IN (1<<16)
1315 /* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
1316 * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
1317 * to the caller, and it should be close() after use. (The fd is a regular
1318 * file descriptor and will be cleaned up on process termination. It holds
1319 * a reference to the request, but nothing else.)
1321 * The sync_file fd can be combined with other sync_file and passed either
1322 * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
1323 * will only occur after this request completes), or to other devices.
1325 * Using I915_EXEC_FENCE_OUT requires use of
1326 * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
1327 * back to userspace. Failure to do so will cause the out-fence to always
1328 * be reported as zero, and the real fence fd to be leaked.
1330 #define I915_EXEC_FENCE_OUT (1<<17)
1333 * Traditionally the execbuf ioctl has only considered the final element in
1334 * the execobject[] to be the executable batch. Often though, the client
1335 * will known the batch object prior to construction and being able to place
1336 * it into the execobject[] array first can simplify the relocation tracking.
1337 * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the
1338 * execobject[] as the * batch instead (the default is to use the last
1341 #define I915_EXEC_BATCH_FIRST (1<<18)
1343 /* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr
1344 * define an array of i915_gem_exec_fence structures which specify a set of
1345 * dma fences to wait upon or signal.
1347 #define I915_EXEC_FENCE_ARRAY (1<<19)
1350 * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
1351 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1354 * Returns -EINVAL if the sync_file fd cannot be found.
1356 #define I915_EXEC_FENCE_SUBMIT (1 << 20)
1359 * Setting I915_EXEC_USE_EXTENSIONS implies that
1360 * drm_i915_gem_execbuffer2.cliprects_ptr is treated as a pointer to an linked
1361 * list of i915_user_extension. Each i915_user_extension node is the base of a
1362 * larger structure. The list of supported structures are listed in the
1363 * drm_i915_gem_execbuffer_ext enum.
1365 #define I915_EXEC_USE_EXTENSIONS (1 << 21)
1367 #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1))
1369 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
1370 #define i915_execbuffer2_set_context_id(eb2, context) \
1371 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
1372 #define i915_execbuffer2_get_context_id(eb2) \
1373 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
1375 struct drm_i915_gem_pin {
1376 /** Handle of the buffer to be pinned. */
1380 /** alignment required within the aperture */
1383 /** Returned GTT offset of the buffer. */
1387 struct drm_i915_gem_unpin {
1388 /** Handle of the buffer to be unpinned. */
1393 struct drm_i915_gem_busy {
1394 /** Handle of the buffer to check for busy */
1397 /** Return busy status
1399 * A return of 0 implies that the object is idle (after
1400 * having flushed any pending activity), and a non-zero return that
1401 * the object is still in-flight on the GPU. (The GPU has not yet
1402 * signaled completion for all pending requests that reference the
1403 * object.) An object is guaranteed to become idle eventually (so
1404 * long as no new GPU commands are executed upon it). Due to the
1405 * asynchronous nature of the hardware, an object reported
1406 * as busy may become idle before the ioctl is completed.
1408 * Furthermore, if the object is busy, which engine is busy is only
1409 * provided as a guide and only indirectly by reporting its class
1410 * (there may be more than one engine in each class). There are race
1411 * conditions which prevent the report of which engines are busy from
1412 * being always accurate. However, the converse is not true. If the
1413 * object is idle, the result of the ioctl, that all engines are idle,
1416 * The returned dword is split into two fields to indicate both
1417 * the engine classess on which the object is being read, and the
1418 * engine class on which it is currently being written (if any).
1420 * The low word (bits 0:15) indicate if the object is being written
1421 * to by any engine (there can only be one, as the GEM implicit
1422 * synchronisation rules force writes to be serialised). Only the
1423 * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
1424 * 1 not 0 etc) for the last write is reported.
1426 * The high word (bits 16:31) are a bitmask of which engines classes
1427 * are currently reading from the object. Multiple engines may be
1428 * reading from the object simultaneously.
1430 * The value of each engine class is the same as specified in the
1431 * I915_CONTEXT_PARAM_ENGINES context parameter and via perf, i.e.
1432 * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
1433 * Some hardware may have parallel execution engines, e.g. multiple
1434 * media engines, which are mapped to the same class identifier and so
1435 * are not separately reported for busyness.
1438 * Only the boolean result of this query is reliable; that is whether
1439 * the object is idle or busy. The report of which engines are busy
1440 * should be only used as a heuristic.
1446 * struct drm_i915_gem_caching - Set or get the caching for given object
1449 * Allow userspace to control the GTT caching bits for a given object when the
1450 * object is later mapped through the ppGTT(or GGTT on older platforms lacking
1451 * ppGTT support, or if the object is used for scanout). Note that this might
1452 * require unbinding the object from the GTT first, if its current caching value
1455 * Note that this all changes on discrete platforms, starting from DG1, the
1456 * set/get caching is no longer supported, and is now rejected. Instead the CPU
1457 * caching attributes(WB vs WC) will become an immutable creation time property
1458 * for the object, along with the GTT caching level. For now we don't expose any
1459 * new uAPI for this, instead on DG1 this is all implicit, although this largely
1460 * shouldn't matter since DG1 is coherent by default(without any way of
1463 * Implicit caching rules, starting from DG1:
1465 * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions)
1466 * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and
1467 * mapped as write-combined only.
1469 * - Everything else is always allocated and mapped as write-back, with the
1470 * guarantee that everything is also coherent with the GPU.
1472 * Note that this is likely to change in the future again, where we might need
1473 * more flexibility on future devices, so making this all explicit as part of a
1474 * new &drm_i915_gem_create_ext extension is probable.
1476 * Side note: Part of the reason for this is that changing the at-allocation-time CPU
1477 * caching attributes for the pages might be required(and is expensive) if we
1478 * need to then CPU map the pages later with different caching attributes. This
1479 * inconsistent caching behaviour, while supported on x86, is not universally
1480 * supported on other architectures. So for simplicity we opt for setting
1481 * everything at creation time, whilst also making it immutable, on discrete
1484 struct drm_i915_gem_caching {
1486 * @handle: Handle of the buffer to set/get the caching level.
1491 * @caching: The GTT caching level to apply or possible return value.
1493 * The supported @caching values:
1495 * I915_CACHING_NONE:
1497 * GPU access is not coherent with CPU caches. Default for machines
1498 * without an LLC. This means manual flushing might be needed, if we
1499 * want GPU access to be coherent.
1501 * I915_CACHING_CACHED:
1503 * GPU access is coherent with CPU caches and furthermore the data is
1504 * cached in last-level caches shared between CPU cores and the GPU GT.
1506 * I915_CACHING_DISPLAY:
1508 * Special GPU caching mode which is coherent with the scanout engines.
1509 * Transparently falls back to I915_CACHING_NONE on platforms where no
1510 * special cache mode (like write-through or gfdt flushing) is
1511 * available. The kernel automatically sets this mode when using a
1512 * buffer as a scanout target. Userspace can manually set this mode to
1513 * avoid a costly stall and clflush in the hotpath of drawing the first
1516 #define I915_CACHING_NONE 0
1517 #define I915_CACHING_CACHED 1
1518 #define I915_CACHING_DISPLAY 2
1522 #define I915_TILING_NONE 0
1523 #define I915_TILING_X 1
1524 #define I915_TILING_Y 2
1525 #define I915_TILING_LAST I915_TILING_Y
1527 #define I915_BIT_6_SWIZZLE_NONE 0
1528 #define I915_BIT_6_SWIZZLE_9 1
1529 #define I915_BIT_6_SWIZZLE_9_10 2
1530 #define I915_BIT_6_SWIZZLE_9_11 3
1531 #define I915_BIT_6_SWIZZLE_9_10_11 4
1532 /* Not seen by userland */
1533 #define I915_BIT_6_SWIZZLE_UNKNOWN 5
1534 /* Seen by userland. */
1535 #define I915_BIT_6_SWIZZLE_9_17 6
1536 #define I915_BIT_6_SWIZZLE_9_10_17 7
1538 struct drm_i915_gem_set_tiling {
1539 /** Handle of the buffer to have its tiling state updated */
1543 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1546 * This value is to be set on request, and will be updated by the
1547 * kernel on successful return with the actual chosen tiling layout.
1549 * The tiling mode may be demoted to I915_TILING_NONE when the system
1550 * has bit 6 swizzling that can't be managed correctly by GEM.
1552 * Buffer contents become undefined when changing tiling_mode.
1557 * Stride in bytes for the object when in I915_TILING_X or
1563 * Returned address bit 6 swizzling required for CPU access through
1569 struct drm_i915_gem_get_tiling {
1570 /** Handle of the buffer to get tiling state for. */
1574 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1580 * Returned address bit 6 swizzling required for CPU access through
1586 * Returned address bit 6 swizzling required for CPU access through
1587 * mmap mapping whilst bound.
1589 __u32 phys_swizzle_mode;
1592 struct drm_i915_gem_get_aperture {
1593 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
1597 * Available space in the aperture used by i915_gem_execbuffer, in
1600 __u64 aper_available_size;
1603 struct drm_i915_get_pipe_from_crtc_id {
1604 /** ID of CRTC being requested **/
1607 /** pipe of requested CRTC **/
1611 #define I915_MADV_WILLNEED 0
1612 #define I915_MADV_DONTNEED 1
1613 #define __I915_MADV_PURGED 2 /* internal state */
1615 struct drm_i915_gem_madvise {
1616 /** Handle of the buffer to change the backing store advice */
1619 /* Advice: either the buffer will be needed again in the near future,
1620 * or wont be and could be discarded under memory pressure.
1624 /** Whether the backing store still exists. */
1629 #define I915_OVERLAY_TYPE_MASK 0xff
1630 #define I915_OVERLAY_YUV_PLANAR 0x01
1631 #define I915_OVERLAY_YUV_PACKED 0x02
1632 #define I915_OVERLAY_RGB 0x03
1634 #define I915_OVERLAY_DEPTH_MASK 0xff00
1635 #define I915_OVERLAY_RGB24 0x1000
1636 #define I915_OVERLAY_RGB16 0x2000
1637 #define I915_OVERLAY_RGB15 0x3000
1638 #define I915_OVERLAY_YUV422 0x0100
1639 #define I915_OVERLAY_YUV411 0x0200
1640 #define I915_OVERLAY_YUV420 0x0300
1641 #define I915_OVERLAY_YUV410 0x0400
1643 #define I915_OVERLAY_SWAP_MASK 0xff0000
1644 #define I915_OVERLAY_NO_SWAP 0x000000
1645 #define I915_OVERLAY_UV_SWAP 0x010000
1646 #define I915_OVERLAY_Y_SWAP 0x020000
1647 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
1649 #define I915_OVERLAY_FLAGS_MASK 0xff000000
1650 #define I915_OVERLAY_ENABLE 0x01000000
1652 struct drm_intel_overlay_put_image {
1653 /* various flags and src format description */
1655 /* source picture description */
1657 /* stride values and offsets are in bytes, buffer relative */
1658 __u16 stride_Y; /* stride for packed formats */
1660 __u32 offset_Y; /* offset for packet formats */
1666 /* to compensate the scaling factors for partially covered surfaces */
1667 __u16 src_scan_width;
1668 __u16 src_scan_height;
1669 /* output crtc description */
1678 #define I915_OVERLAY_UPDATE_ATTRS (1<<0)
1679 #define I915_OVERLAY_UPDATE_GAMMA (1<<1)
1680 #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
1681 struct drm_intel_overlay_attrs {
1696 * Intel sprite handling
1698 * Color keying works with a min/mask/max tuple. Both source and destination
1699 * color keying is allowed.
1702 * Sprite pixels within the min & max values, masked against the color channels
1703 * specified in the mask field, will be transparent. All other pixels will
1704 * be displayed on top of the primary plane. For RGB surfaces, only the min
1705 * and mask fields will be used; ranged compares are not allowed.
1707 * Destination keying:
1708 * Primary plane pixels that match the min value, masked against the color
1709 * channels specified in the mask field, will be replaced by corresponding
1710 * pixels from the sprite plane.
1712 * Note that source & destination keying are exclusive; only one can be
1713 * active on a given plane.
1716 #define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set
1717 * flags==0 to disable colorkeying.
1719 #define I915_SET_COLORKEY_DESTINATION (1<<1)
1720 #define I915_SET_COLORKEY_SOURCE (1<<2)
1721 struct drm_intel_sprite_colorkey {
1729 struct drm_i915_gem_wait {
1730 /** Handle of BO we shall wait on */
1733 /** Number of nanoseconds to wait, Returns time remaining. */
1737 struct drm_i915_gem_context_create {
1738 __u32 ctx_id; /* output: id of new context*/
1742 struct drm_i915_gem_context_create_ext {
1743 __u32 ctx_id; /* output: id of new context*/
1745 #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
1746 #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)
1747 #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
1748 (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
1752 struct drm_i915_gem_context_param {
1756 #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1757 /* I915_CONTEXT_PARAM_NO_ZEROMAP has been removed. On the off chance
1758 * someone somewhere has attempted to use it, never re-use this context
1761 #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1762 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1763 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
1764 #define I915_CONTEXT_PARAM_BANNABLE 0x5
1765 #define I915_CONTEXT_PARAM_PRIORITY 0x6
1766 #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
1767 #define I915_CONTEXT_DEFAULT_PRIORITY 0
1768 #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
1770 * When using the following param, value should be a pointer to
1771 * drm_i915_gem_context_param_sseu.
1773 #define I915_CONTEXT_PARAM_SSEU 0x7
1776 * Not all clients may want to attempt automatic recover of a context after
1777 * a hang (for example, some clients may only submit very small incremental
1778 * batches relying on known logical state of previous batches which will never
1779 * recover correctly and each attempt will hang), and so would prefer that
1780 * the context is forever banned instead.
1782 * If set to false (0), after a reset, subsequent (and in flight) rendering
1783 * from this context is discarded, and the client will need to create a new
1784 * context to use instead.
1786 * If set to true (1), the kernel will automatically attempt to recover the
1787 * context by skipping the hanging batch and executing the next batch starting
1788 * from the default context state (discarding the incomplete logical context
1789 * state lost due to the reset).
1791 * On creation, all new contexts are marked as recoverable.
1793 #define I915_CONTEXT_PARAM_RECOVERABLE 0x8
1796 * The id of the associated virtual memory address space (ppGTT) of
1797 * this context. Can be retrieved and passed to another context
1798 * (on the same fd) for both to use the same ppGTT and so share
1799 * address layouts, and avoid reloading the page tables on context
1800 * switches between themselves.
1802 * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
1804 #define I915_CONTEXT_PARAM_VM 0x9
1807 * I915_CONTEXT_PARAM_ENGINES:
1809 * Bind this context to operate on this subset of available engines. Henceforth,
1810 * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
1811 * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
1812 * and upwards. Slots 0...N are filled in using the specified (class, instance).
1814 * engine_class: I915_ENGINE_CLASS_INVALID,
1815 * engine_instance: I915_ENGINE_CLASS_INVALID_NONE
1816 * to specify a gap in the array that can be filled in later, e.g. by a
1817 * virtual engine used for load balancing.
1819 * Setting the number of engines bound to the context to 0, by passing a zero
1820 * sized argument, will revert back to default settings.
1822 * See struct i915_context_param_engines.
1825 * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
1826 * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
1828 #define I915_CONTEXT_PARAM_ENGINES 0xa
1831 * I915_CONTEXT_PARAM_PERSISTENCE:
1833 * Allow the context and active rendering to survive the process until
1834 * completion. Persistence allows fire-and-forget clients to queue up a
1835 * bunch of work, hand the output over to a display server and then quit.
1836 * If the context is marked as not persistent, upon closing (either via
1837 * an explicit DRM_I915_GEM_CONTEXT_DESTROY or implicitly from file closure
1838 * or process termination), the context and any outstanding requests will be
1839 * cancelled (and exported fences for cancelled requests marked as -EIO).
1841 * By default, new contexts allow persistence.
1843 #define I915_CONTEXT_PARAM_PERSISTENCE 0xb
1845 /* This API has been removed. On the off chance someone somewhere has
1846 * attempted to use it, never re-use this context param number.
1848 #define I915_CONTEXT_PARAM_RINGSIZE 0xc
1849 /* Must be kept compact -- no holes and well documented */
1855 * Context SSEU programming
1857 * It may be necessary for either functional or performance reason to configure
1858 * a context to run with a reduced number of SSEU (where SSEU stands for Slice/
1861 * This is done by configuring SSEU configuration using the below
1862 * @struct drm_i915_gem_context_param_sseu for every supported engine which
1863 * userspace intends to use.
1865 * Not all GPUs or engines support this functionality in which case an error
1866 * code -ENODEV will be returned.
1868 * Also, flexibility of possible SSEU configuration permutations varies between
1869 * GPU generations and software imposed limitations. Requesting such a
1870 * combination will return an error code of -EINVAL.
1872 * NOTE: When perf/OA is active the context's SSEU configuration is ignored in
1873 * favour of a single global setting.
1875 struct drm_i915_gem_context_param_sseu {
1877 * Engine class & instance to be configured or queried.
1879 struct i915_engine_class_instance engine;
1882 * Unknown flags must be cleared to zero.
1885 #define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
1888 * Mask of slices to enable for the context. Valid values are a subset
1889 * of the bitmask value returned for I915_PARAM_SLICE_MASK.
1894 * Mask of subslices to enable for the context. Valid values are a
1895 * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
1897 __u64 subslice_mask;
1900 * Minimum/Maximum number of EUs to enable per subslice for the
1901 * context. min_eus_per_subslice must be inferior or equal to
1902 * max_eus_per_subslice.
1904 __u16 min_eus_per_subslice;
1905 __u16 max_eus_per_subslice;
1908 * Unused for now. Must be cleared to zero.
1914 * DOC: Virtual Engine uAPI
1916 * Virtual engine is a concept where userspace is able to configure a set of
1917 * physical engines, submit a batch buffer, and let the driver execute it on any
1918 * engine from the set as it sees fit.
1920 * This is primarily useful on parts which have multiple instances of a same
1921 * class engine, like for example GT3+ Skylake parts with their two VCS engines.
1923 * For instance userspace can enumerate all engines of a certain class using the
1924 * previously described `Engine Discovery uAPI`_. After that userspace can
1925 * create a GEM context with a placeholder slot for the virtual engine (using
1926 * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class
1927 * and instance respectively) and finally using the
1928 * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in
1929 * the same reserved slot.
1931 * Example of creating a virtual engine and submitting a batch buffer to it:
1935 * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = {
1936 * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE,
1937 * .engine_index = 0, // Place this virtual engine into engine map slot 0
1938 * .num_siblings = 2,
1939 * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 },
1940 * { I915_ENGINE_CLASS_VIDEO, 1 }, },
1942 * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
1943 * .engines = { { I915_ENGINE_CLASS_INVALID,
1944 * I915_ENGINE_CLASS_INVALID_NONE } },
1945 * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension
1947 * struct drm_i915_gem_context_create_ext_setparam p_engines = {
1949 * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
1952 * .param = I915_CONTEXT_PARAM_ENGINES,
1953 * .value = to_user_pointer(&engines),
1954 * .size = sizeof(engines),
1957 * struct drm_i915_gem_context_create_ext create = {
1958 * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
1959 * .extensions = to_user_pointer(&p_engines);
1962 * ctx_id = gem_context_create_ext(drm_fd, &create);
1964 * // Now we have created a GEM context with its engine map containing a
1965 * // single virtual engine. Submissions to this slot can go either to
1966 * // vcs0 or vcs1, depending on the load balancing algorithm used inside
1967 * // the driver. The load balancing is dynamic from one batch buffer to
1968 * // another and transparent to userspace.
1971 * execbuf.rsvd1 = ctx_id;
1972 * execbuf.flags = 0; // Submits to index 0 which is the virtual engine
1973 * gem_execbuf(drm_fd, &execbuf);
1977 * i915_context_engines_load_balance:
1979 * Enable load balancing across this set of engines.
1981 * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
1982 * used will proxy the execbuffer request onto one of the set of engines
1983 * in such a way as to distribute the load evenly across the set.
1985 * The set of engines must be compatible (e.g. the same HW class) as they
1986 * will share the same logical GPU context and ring.
1988 * To intermix rendering with the virtual engine and direct rendering onto
1989 * the backing engines (bypassing the load balancing proxy), the context must
1990 * be defined to use a single timeline for all engines.
1992 struct i915_context_engines_load_balance {
1993 struct i915_user_extension base;
1997 __u32 flags; /* all undefined flags must be zero */
1999 __u64 mbz64; /* reserved for future use; must be zero */
2001 struct i915_engine_class_instance engines[0];
2002 } __attribute__((packed));
2004 #define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \
2005 struct i915_user_extension base; \
2006 __u16 engine_index; \
2007 __u16 num_siblings; \
2010 struct i915_engine_class_instance engines[N__]; \
2011 } __attribute__((packed)) name__
2014 * i915_context_engines_bond:
2016 * Constructed bonded pairs for execution within a virtual engine.
2018 * All engines are equal, but some are more equal than others. Given
2019 * the distribution of resources in the HW, it may be preferable to run
2020 * a request on a given subset of engines in parallel to a request on a
2021 * specific engine. We enable this selection of engines within a virtual
2022 * engine by specifying bonding pairs, for any given master engine we will
2023 * only execute on one of the corresponding siblings within the virtual engine.
2025 * To execute a request in parallel on the master engine and a sibling requires
2026 * coordination with a I915_EXEC_FENCE_SUBMIT.
2028 struct i915_context_engines_bond {
2029 struct i915_user_extension base;
2031 struct i915_engine_class_instance master;
2033 __u16 virtual_index; /* index of virtual engine in ctx->engines[] */
2036 __u64 flags; /* all undefined flags must be zero */
2037 __u64 mbz64[4]; /* reserved for future use; must be zero */
2039 struct i915_engine_class_instance engines[0];
2040 } __attribute__((packed));
2042 #define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \
2043 struct i915_user_extension base; \
2044 struct i915_engine_class_instance master; \
2045 __u16 virtual_index; \
2049 struct i915_engine_class_instance engines[N__]; \
2050 } __attribute__((packed)) name__
2053 * DOC: Context Engine Map uAPI
2055 * Context engine map is a new way of addressing engines when submitting batch-
2056 * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT`
2057 * inside the flags field of `struct drm_i915_gem_execbuffer2`.
2059 * To use it created GEM contexts need to be configured with a list of engines
2060 * the user is intending to submit to. This is accomplished using the
2061 * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct
2062 * i915_context_param_engines`.
2064 * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the
2067 * Example of creating such context and submitting against it:
2071 * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = {
2072 * .engines = { { I915_ENGINE_CLASS_RENDER, 0 },
2073 * { I915_ENGINE_CLASS_COPY, 0 } }
2075 * struct drm_i915_gem_context_create_ext_setparam p_engines = {
2077 * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
2080 * .param = I915_CONTEXT_PARAM_ENGINES,
2081 * .value = to_user_pointer(&engines),
2082 * .size = sizeof(engines),
2085 * struct drm_i915_gem_context_create_ext create = {
2086 * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
2087 * .extensions = to_user_pointer(&p_engines);
2090 * ctx_id = gem_context_create_ext(drm_fd, &create);
2092 * // We have now created a GEM context with two engines in the map:
2093 * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines
2094 * // will not be accessible from this context.
2097 * execbuf.rsvd1 = ctx_id;
2098 * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context
2099 * gem_execbuf(drm_fd, &execbuf);
2102 * execbuf.rsvd1 = ctx_id;
2103 * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context
2104 * gem_execbuf(drm_fd, &execbuf);
2107 struct i915_context_param_engines {
2108 __u64 extensions; /* linked chain of extension blocks, 0 terminates */
2109 #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
2110 #define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
2111 struct i915_engine_class_instance engines[0];
2112 } __attribute__((packed));
2114 #define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
2116 struct i915_engine_class_instance engines[N__]; \
2117 } __attribute__((packed)) name__
2119 struct drm_i915_gem_context_create_ext_setparam {
2120 #define I915_CONTEXT_CREATE_EXT_SETPARAM 0
2121 struct i915_user_extension base;
2122 struct drm_i915_gem_context_param param;
2125 /* This API has been removed. On the off chance someone somewhere has
2126 * attempted to use it, never re-use this extension number.
2128 #define I915_CONTEXT_CREATE_EXT_CLONE 1
2130 struct drm_i915_gem_context_destroy {
2136 * DRM_I915_GEM_VM_CREATE -
2138 * Create a new virtual memory address space (ppGTT) for use within a context
2139 * on the same file. Extensions can be provided to configure exactly how the
2140 * address space is setup upon creation.
2142 * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
2143 * returned in the outparam @id.
2145 * No flags are defined, with all bits reserved and must be zero.
2147 * An extension chain maybe provided, starting with @extensions, and terminated
2148 * by the @next_extension being 0. Currently, no extensions are defined.
2150 * DRM_I915_GEM_VM_DESTROY -
2152 * Destroys a previously created VM id, specified in @id.
2154 * No extensions or flags are allowed currently, and so must be zero.
2156 struct drm_i915_gem_vm_control {
2162 struct drm_i915_reg_read {
2165 * For 64bit wide registers where the upper 32bits don't immediately
2166 * follow the lower 32bits, the offset of the lower 32bits must
2170 #define I915_REG_READ_8B_WA (1ul << 0)
2172 __u64 val; /* Return value */
2177 * Render engine timestamp - 0x2358 + 64bit - gen7+
2178 * - Note this register returns an invalid value if using the default
2179 * single instruction 8byte read, in order to workaround that pass
2180 * flag I915_REG_READ_8B_WA in offset field.
2184 struct drm_i915_reset_stats {
2188 /* All resets since boot/module reload, for all contexts */
2191 /* Number of batches lost when active in GPU, for this context */
2194 /* Number of batches lost pending for execution, for this context */
2195 __u32 batch_pending;
2201 * struct drm_i915_gem_userptr - Create GEM object from user allocated memory.
2203 * Userptr objects have several restrictions on what ioctls can be used with the
2206 struct drm_i915_gem_userptr {
2208 * @user_ptr: The pointer to the allocated memory.
2210 * Needs to be aligned to PAGE_SIZE.
2217 * The size in bytes for the allocated memory. This will also become the
2220 * Needs to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE,
2230 * I915_USERPTR_READ_ONLY:
2232 * Mark the object as readonly, this also means GPU access can only be
2233 * readonly. This is only supported on HW which supports readonly access
2234 * through the GTT. If the HW can't support readonly access, an error is
2237 * I915_USERPTR_PROBE:
2239 * Probe the provided @user_ptr range and validate that the @user_ptr is
2240 * indeed pointing to normal memory and that the range is also valid.
2241 * For example if some garbage address is given to the kernel, then this
2244 * Returns -EFAULT if the probe failed.
2246 * Note that this doesn't populate the backing pages, and also doesn't
2247 * guarantee that the object will remain valid when the object is
2250 * The kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE
2251 * returns a non-zero value.
2253 * I915_USERPTR_UNSYNCHRONIZED:
2255 * NOT USED. Setting this flag will result in an error.
2258 #define I915_USERPTR_READ_ONLY 0x1
2259 #define I915_USERPTR_PROBE 0x2
2260 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000
2262 * @handle: Returned handle for the object.
2264 * Object handles are nonzero.
2269 enum drm_i915_oa_format {
2270 I915_OA_FORMAT_A13 = 1, /* HSW only */
2271 I915_OA_FORMAT_A29, /* HSW only */
2272 I915_OA_FORMAT_A13_B8_C8, /* HSW only */
2273 I915_OA_FORMAT_B4_C8, /* HSW only */
2274 I915_OA_FORMAT_A45_B8_C8, /* HSW only */
2275 I915_OA_FORMAT_B4_C8_A16, /* HSW only */
2276 I915_OA_FORMAT_C4_B8, /* HSW+ */
2280 I915_OA_FORMAT_A12_B8_C8,
2281 I915_OA_FORMAT_A32u40_A4u32_B8_C8,
2283 I915_OA_FORMAT_MAX /* non-ABI */
2286 enum drm_i915_perf_property_id {
2288 * Open the stream for a specific context handle (as used with
2289 * execbuffer2). A stream opened for a specific context this way
2290 * won't typically require root privileges.
2292 * This property is available in perf revision 1.
2294 DRM_I915_PERF_PROP_CTX_HANDLE = 1,
2297 * A value of 1 requests the inclusion of raw OA unit reports as
2298 * part of stream samples.
2300 * This property is available in perf revision 1.
2302 DRM_I915_PERF_PROP_SAMPLE_OA,
2305 * The value specifies which set of OA unit metrics should be
2306 * configured, defining the contents of any OA unit reports.
2308 * This property is available in perf revision 1.
2310 DRM_I915_PERF_PROP_OA_METRICS_SET,
2313 * The value specifies the size and layout of OA unit reports.
2315 * This property is available in perf revision 1.
2317 DRM_I915_PERF_PROP_OA_FORMAT,
2320 * Specifying this property implicitly requests periodic OA unit
2321 * sampling and (at least on Haswell) the sampling frequency is derived
2322 * from this exponent as follows:
2324 * 80ns * 2^(period_exponent + 1)
2326 * This property is available in perf revision 1.
2328 DRM_I915_PERF_PROP_OA_EXPONENT,
2331 * Specifying this property is only valid when specify a context to
2332 * filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property
2333 * will hold preemption of the particular context we want to gather
2334 * performance data about. The execbuf2 submissions must include a
2335 * drm_i915_gem_execbuffer_ext_perf parameter for this to apply.
2337 * This property is available in perf revision 3.
2339 DRM_I915_PERF_PROP_HOLD_PREEMPTION,
2342 * Specifying this pins all contexts to the specified SSEU power
2343 * configuration for the duration of the recording.
2345 * This parameter's value is a pointer to a struct
2346 * drm_i915_gem_context_param_sseu.
2348 * This property is available in perf revision 4.
2350 DRM_I915_PERF_PROP_GLOBAL_SSEU,
2353 * This optional parameter specifies the timer interval in nanoseconds
2354 * at which the i915 driver will check the OA buffer for available data.
2355 * Minimum allowed value is 100 microseconds. A default value is used by
2356 * the driver if this parameter is not specified. Note that larger timer
2357 * values will reduce cpu consumption during OA perf captures. However,
2358 * excessively large values would potentially result in OA buffer
2359 * overwrites as captures reach end of the OA buffer.
2361 * This property is available in perf revision 5.
2363 DRM_I915_PERF_PROP_POLL_OA_PERIOD,
2365 DRM_I915_PERF_PROP_MAX /* non-ABI */
2368 struct drm_i915_perf_open_param {
2370 #define I915_PERF_FLAG_FD_CLOEXEC (1<<0)
2371 #define I915_PERF_FLAG_FD_NONBLOCK (1<<1)
2372 #define I915_PERF_FLAG_DISABLED (1<<2)
2374 /** The number of u64 (id, value) pairs */
2375 __u32 num_properties;
2378 * Pointer to array of u64 (id, value) pairs configuring the stream
2381 __u64 properties_ptr;
2385 * Enable data capture for a stream that was either opened in a disabled state
2386 * via I915_PERF_FLAG_DISABLED or was later disabled via
2387 * I915_PERF_IOCTL_DISABLE.
2389 * It is intended to be cheaper to disable and enable a stream than it may be
2390 * to close and re-open a stream with the same configuration.
2392 * It's undefined whether any pending data for the stream will be lost.
2394 * This ioctl is available in perf revision 1.
2396 #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
2399 * Disable data capture for a stream.
2401 * It is an error to try and read a stream that is disabled.
2403 * This ioctl is available in perf revision 1.
2405 #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
2408 * Change metrics_set captured by a stream.
2410 * If the stream is bound to a specific context, the configuration change
2411 * will performed inline with that context such that it takes effect before
2412 * the next execbuf submission.
2414 * Returns the previously bound metrics set id, or a negative error code.
2416 * This ioctl is available in perf revision 2.
2418 #define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
2421 * Common to all i915 perf records
2423 struct drm_i915_perf_record_header {
2429 enum drm_i915_perf_record_type {
2432 * Samples are the work horse record type whose contents are extensible
2433 * and defined when opening an i915 perf stream based on the given
2436 * Boolean properties following the naming convention
2437 * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
2440 * The order of these sample properties given by userspace has no
2441 * affect on the ordering of data within a sample. The order is
2445 * struct drm_i915_perf_record_header header;
2447 * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
2450 DRM_I915_PERF_RECORD_SAMPLE = 1,
2453 * Indicates that one or more OA reports were not written by the
2454 * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
2455 * command collides with periodic sampling - which would be more likely
2456 * at higher sampling frequencies.
2458 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
2461 * An error occurred that resulted in all pending OA reports being lost.
2463 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
2465 DRM_I915_PERF_RECORD_MAX /* non-ABI */
2469 * Structure to upload perf dynamic configuration into the kernel.
2471 struct drm_i915_perf_oa_config {
2472 /** String formatted like "%08x-%04x-%04x-%04x-%012x" */
2476 __u32 n_boolean_regs;
2480 * These fields are pointers to tuples of u32 values (register address,
2481 * value). For example the expected length of the buffer pointed by
2482 * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
2485 __u64 boolean_regs_ptr;
2486 __u64 flex_regs_ptr;
2490 * struct drm_i915_query_item - An individual query for the kernel to process.
2492 * The behaviour is determined by the @query_id. Note that exactly what
2493 * @data_ptr is also depends on the specific @query_id.
2495 struct drm_i915_query_item {
2496 /** @query_id: The id for this query */
2498 #define DRM_I915_QUERY_TOPOLOGY_INFO 1
2499 #define DRM_I915_QUERY_ENGINE_INFO 2
2500 #define DRM_I915_QUERY_PERF_CONFIG 3
2501 #define DRM_I915_QUERY_MEMORY_REGIONS 4
2502 /* Must be kept compact -- no holes and well documented */
2507 * When set to zero by userspace, this is filled with the size of the
2508 * data to be written at the @data_ptr pointer. The kernel sets this
2509 * value to a negative value to signal an error on a particular query
2517 * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
2519 * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
2522 * - DRM_I915_QUERY_PERF_CONFIG_LIST
2523 * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
2524 * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
2527 #define DRM_I915_QUERY_PERF_CONFIG_LIST 1
2528 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
2529 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3
2534 * Data will be written at the location pointed by @data_ptr when the
2535 * value of @length matches the length of the data to be written by the
2542 * struct drm_i915_query - Supply an array of struct drm_i915_query_item for the
2543 * kernel to fill out.
2545 * Note that this is generally a two step process for each struct
2546 * drm_i915_query_item in the array:
2548 * 1. Call the DRM_IOCTL_I915_QUERY, giving it our array of struct
2549 * drm_i915_query_item, with &drm_i915_query_item.length set to zero. The
2550 * kernel will then fill in the size, in bytes, which tells userspace how
2551 * memory it needs to allocate for the blob(say for an array of properties).
2553 * 2. Next we call DRM_IOCTL_I915_QUERY again, this time with the
2554 * &drm_i915_query_item.data_ptr equal to our newly allocated blob. Note that
2555 * the &drm_i915_query_item.length should still be the same as what the
2556 * kernel previously set. At this point the kernel can fill in the blob.
2558 * Note that for some query items it can make sense for userspace to just pass
2559 * in a buffer/blob equal to or larger than the required size. In this case only
2560 * a single ioctl call is needed. For some smaller query items this can work
2564 struct drm_i915_query {
2565 /** @num_items: The number of elements in the @items_ptr array */
2569 * @flags: Unused for now. Must be cleared to zero.
2576 * Pointer to an array of struct drm_i915_query_item. The number of
2577 * array elements is @num_items.
2583 * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
2585 * data: contains the 3 pieces of information :
2587 * - the slice mask with one bit per slice telling whether a slice is
2588 * available. The availability of slice X can be queried with the following
2591 * (data[X / 8] >> (X % 8)) & 1
2593 * - the subslice mask for each slice with one bit per subslice telling
2594 * whether a subslice is available. Gen12 has dual-subslices, which are
2595 * similar to two gen11 subslices. For gen12, this array represents dual-
2596 * subslices. The availability of subslice Y in slice X can be queried
2597 * with the following formula :
2599 * (data[subslice_offset +
2600 * X * subslice_stride +
2601 * Y / 8] >> (Y % 8)) & 1
2603 * - the EU mask for each subslice in each slice with one bit per EU telling
2604 * whether an EU is available. The availability of EU Z in subslice Y in
2605 * slice X can be queried with the following formula :
2608 * (X * max_subslices + Y) * eu_stride +
2609 * Z / 8] >> (Z % 8)) & 1
2611 struct drm_i915_query_topology_info {
2613 * Unused for now. Must be cleared to zero.
2618 __u16 max_subslices;
2619 __u16 max_eus_per_subslice;
2622 * Offset in data[] at which the subslice masks are stored.
2624 __u16 subslice_offset;
2627 * Stride at which each of the subslice masks for each slice are
2630 __u16 subslice_stride;
2633 * Offset in data[] at which the EU masks are stored.
2638 * Stride at which each of the EU masks for each subslice are stored.
2646 * DOC: Engine Discovery uAPI
2648 * Engine discovery uAPI is a way of enumerating physical engines present in a
2649 * GPU associated with an open i915 DRM file descriptor. This supersedes the old
2650 * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like
2651 * `I915_PARAM_HAS_BLT`.
2653 * The need for this interface came starting with Icelake and newer GPUs, which
2654 * started to establish a pattern of having multiple engines of a same class,
2655 * where not all instances were always completely functionally equivalent.
2657 * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the
2658 * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id.
2660 * Example for getting the list of engines:
2664 * struct drm_i915_query_engine_info *info;
2665 * struct drm_i915_query_item item = {
2666 * .query_id = DRM_I915_QUERY_ENGINE_INFO;
2668 * struct drm_i915_query query = {
2670 * .items_ptr = (uintptr_t)&item,
2674 * // First query the size of the blob we need, this needs to be large
2675 * // enough to hold our array of engines. The kernel will fill out the
2676 * // item.length for us, which is the number of bytes we need.
2678 * // Alternatively a large buffer can be allocated straight away enabling
2679 * // querying in one pass, in which case item.length should contain the
2680 * // length of the provided buffer.
2681 * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
2684 * info = calloc(1, item.length);
2685 * // Now that we allocated the required number of bytes, we call the ioctl
2686 * // again, this time with the data_ptr pointing to our newly allocated
2687 * // blob, which the kernel can then populate with info on all engines.
2688 * item.data_ptr = (uintptr_t)&info,
2690 * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
2693 * // We can now access each engine in the array
2694 * for (i = 0; i < info->num_engines; i++) {
2695 * struct drm_i915_engine_info einfo = info->engines[i];
2696 * u16 class = einfo.engine.class;
2697 * u16 instance = einfo.engine.instance;
2703 * Each of the enumerated engines, apart from being defined by its class and
2704 * instance (see `struct i915_engine_class_instance`), also can have flags and
2705 * capabilities defined as documented in i915_drm.h.
2707 * For instance video engines which support HEVC encoding will have the
2708 * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set.
2710 * Engine discovery only fully comes to its own when combined with the new way
2711 * of addressing engines when submitting batch buffers using contexts with
2712 * engine maps configured.
2716 * struct drm_i915_engine_info
2718 * Describes one engine and it's capabilities as known to the driver.
2720 struct drm_i915_engine_info {
2721 /** @engine: Engine class and instance. */
2722 struct i915_engine_class_instance engine;
2724 /** @rsvd0: Reserved field. */
2727 /** @flags: Engine flags. */
2730 /** @capabilities: Capabilities of this engine. */
2732 #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
2733 #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
2735 /** @rsvd1: Reserved fields. */
2740 * struct drm_i915_query_engine_info
2742 * Engine info query enumerates all engines known to the driver by filling in
2743 * an array of struct drm_i915_engine_info structures.
2745 struct drm_i915_query_engine_info {
2746 /** @num_engines: Number of struct drm_i915_engine_info structs following. */
2752 /** @engines: Marker for drm_i915_engine_info structures. */
2753 struct drm_i915_engine_info engines[];
2757 * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
2759 struct drm_i915_query_perf_config {
2762 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
2763 * this fields to the number of configurations available.
2768 * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
2769 * i915 will use the value in this field as configuration
2770 * identifier to decide what data to write into config_ptr.
2775 * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
2776 * i915 will use the value in this field as configuration
2777 * identifier to decide what data to write into config_ptr.
2779 * String formatted like "%08x-%04x-%04x-%04x-%012x"
2785 * Unused for now. Must be cleared to zero.
2790 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
2791 * write an array of __u64 of configuration identifiers.
2793 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
2794 * write a struct drm_i915_perf_oa_config. If the following fields of
2795 * drm_i915_perf_oa_config are set not set to 0, i915 will write into
2796 * the associated pointers the values of submitted when the
2797 * configuration was created :
2807 * enum drm_i915_gem_memory_class - Supported memory classes
2809 enum drm_i915_gem_memory_class {
2810 /** @I915_MEMORY_CLASS_SYSTEM: System memory */
2811 I915_MEMORY_CLASS_SYSTEM = 0,
2812 /** @I915_MEMORY_CLASS_DEVICE: Device local-memory */
2813 I915_MEMORY_CLASS_DEVICE,
2817 * struct drm_i915_gem_memory_class_instance - Identify particular memory region
2819 struct drm_i915_gem_memory_class_instance {
2820 /** @memory_class: See enum drm_i915_gem_memory_class */
2823 /** @memory_instance: Which instance */
2824 __u16 memory_instance;
2828 * struct drm_i915_memory_region_info - Describes one region as known to the
2831 * Note that we reserve some stuff here for potential future work. As an example
2832 * we might want expose the capabilities for a given region, which could include
2833 * things like if the region is CPU mappable/accessible, what are the supported
2834 * mapping types etc.
2836 * Note that to extend struct drm_i915_memory_region_info and struct
2837 * drm_i915_query_memory_regions in the future the plan is to do the following:
2841 * struct drm_i915_memory_region_info {
2842 * struct drm_i915_gem_memory_class_instance region;
2858 * With this things should remain source compatible between versions for
2859 * userspace, even as we add new fields.
2861 * Note this is using both struct drm_i915_query_item and struct drm_i915_query.
2862 * For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS
2863 * at &drm_i915_query_item.query_id.
2865 struct drm_i915_memory_region_info {
2866 /** @region: The class:instance pair encoding */
2867 struct drm_i915_gem_memory_class_instance region;
2872 /** @probed_size: Memory probed by the driver (-1 = unknown) */
2875 /** @unallocated_size: Estimate of memory remaining (-1 = unknown) */
2876 __u64 unallocated_size;
2883 * struct drm_i915_query_memory_regions
2885 * The region info query enumerates all regions known to the driver by filling
2886 * in an array of struct drm_i915_memory_region_info structures.
2888 * Example for getting the list of supported regions:
2892 * struct drm_i915_query_memory_regions *info;
2893 * struct drm_i915_query_item item = {
2894 * .query_id = DRM_I915_QUERY_MEMORY_REGIONS;
2896 * struct drm_i915_query query = {
2898 * .items_ptr = (uintptr_t)&item,
2902 * // First query the size of the blob we need, this needs to be large
2903 * // enough to hold our array of regions. The kernel will fill out the
2904 * // item.length for us, which is the number of bytes we need.
2905 * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
2908 * info = calloc(1, item.length);
2909 * // Now that we allocated the required number of bytes, we call the ioctl
2910 * // again, this time with the data_ptr pointing to our newly allocated
2911 * // blob, which the kernel can then populate with the all the region info.
2912 * item.data_ptr = (uintptr_t)&info,
2914 * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
2917 * // We can now access each region in the array
2918 * for (i = 0; i < info->num_regions; i++) {
2919 * struct drm_i915_memory_region_info mr = info->regions[i];
2920 * u16 class = mr.region.class;
2921 * u16 instance = mr.region.instance;
2928 struct drm_i915_query_memory_regions {
2929 /** @num_regions: Number of supported regions */
2935 /** @regions: Info about each supported region */
2936 struct drm_i915_memory_region_info regions[];
2940 * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
2941 * extension support using struct i915_user_extension.
2943 * Note that in the future we want to have our buffer flags here, at least for
2944 * the stuff that is immutable. Previously we would have two ioctls, one to
2945 * create the object with gem_create, and another to apply various parameters,
2946 * however this creates some ambiguity for the params which are considered
2947 * immutable. Also in general we're phasing out the various SET/GET ioctls.
2949 struct drm_i915_gem_create_ext {
2951 * @size: Requested size for the object.
2953 * The (page-aligned) allocated size for the object will be returned.
2955 * Note that for some devices we have might have further minimum
2956 * page-size restrictions(larger than 4K), like for device local-memory.
2957 * However in general the final size here should always reflect any
2958 * rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS
2959 * extension to place the object in device local-memory.
2963 * @handle: Returned handle for the object.
2965 * Object handles are nonzero.
2971 * @extensions: The chain of extensions to apply to this object.
2973 * This will be useful in the future when we need to support several
2974 * different extensions, and we need to apply more than one when
2975 * creating the object. See struct i915_user_extension.
2977 * If we don't supply any extensions then we get the same old gem_create
2980 * For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see
2981 * struct drm_i915_gem_create_ext_memory_regions.
2983 #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
2988 * struct drm_i915_gem_create_ext_memory_regions - The
2989 * I915_GEM_CREATE_EXT_MEMORY_REGIONS extension.
2991 * Set the object with the desired set of placements/regions in priority
2992 * order. Each entry must be unique and supported by the device.
2994 * This is provided as an array of struct drm_i915_gem_memory_class_instance, or
2995 * an equivalent layout of class:instance pair encodings. See struct
2996 * drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to
2997 * query the supported regions for a device.
2999 * As an example, on discrete devices, if we wish to set the placement as
3000 * device local-memory we can do something like:
3004 * struct drm_i915_gem_memory_class_instance region_lmem = {
3005 * .memory_class = I915_MEMORY_CLASS_DEVICE,
3006 * .memory_instance = 0,
3008 * struct drm_i915_gem_create_ext_memory_regions regions = {
3009 * .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS },
3010 * .regions = (uintptr_t)®ion_lmem,
3013 * struct drm_i915_gem_create_ext create_ext = {
3014 * .size = 16 * PAGE_SIZE,
3015 * .extensions = (uintptr_t)®ions,
3018 * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
3021 * At which point we get the object handle in &drm_i915_gem_create_ext.handle,
3022 * along with the final object size in &drm_i915_gem_create_ext.size, which
3023 * should account for any rounding up, if required.
3025 struct drm_i915_gem_create_ext_memory_regions {
3026 /** @base: Extension link. See struct i915_user_extension. */
3027 struct i915_user_extension base;
3031 /** @num_regions: Number of elements in the @regions array. */
3034 * @regions: The regions/placements array.
3036 * An array of struct drm_i915_gem_memory_class_instance.
3041 #if defined(__cplusplus)
3045 #endif /* _UAPI_I915_DRM_H_ */