include/linux/nvme.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Definitions for the NVM Express interface
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #ifndef _LINUX_NVME_H
   8 #define _LINUX_NVME_H
   9
  10 #include <linux/types.h>
  11 #include <linux/uuid.h>
  12
  13 /* NQN names in commands fields specified one size */
  14 #define NVMF_NQN_FIELD_LEN      256
  15
  16 /* However the max length of a qualified name is another size */
  17 #define NVMF_NQN_SIZE           223
  18
  19 #define NVMF_TRSVCID_SIZE       32
  20 #define NVMF_TRADDR_SIZE        256
  21 #define NVMF_TSAS_SIZE          256
  22
  23 #define NVME_DISC_SUBSYS_NAME   "nqn.2014-08.org.nvmexpress.discovery"
  24
  25 #define NVME_RDMA_IP_PORT       4420
  26
  27 #define NVME_NSID_ALL           0xffffffff
  28
  29 enum nvme_subsys_type {
  30         NVME_NQN_DISC   = 1,            /* Discovery type target subsystem */
  31         NVME_NQN_NVME   = 2,            /* NVME type target subsystem */
  32 };
  33
  34 /* Address Family codes for Discovery Log Page entry ADRFAM field */
  35 enum {
  36         NVMF_ADDR_FAMILY_PCI    = 0,    /* PCIe */
  37         NVMF_ADDR_FAMILY_IP4    = 1,    /* IP4 */
  38         NVMF_ADDR_FAMILY_IP6    = 2,    /* IP6 */
  39         NVMF_ADDR_FAMILY_IB     = 3,    /* InfiniBand */
  40         NVMF_ADDR_FAMILY_FC     = 4,    /* Fibre Channel */
  41         NVMF_ADDR_FAMILY_LOOP   = 254,  /* Reserved for host usage */
  42         NVMF_ADDR_FAMILY_MAX,
  43 };
  44
  45 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
  46 enum {
  47         NVMF_TRTYPE_RDMA        = 1,    /* RDMA */
  48         NVMF_TRTYPE_FC          = 2,    /* Fibre Channel */
  49         NVMF_TRTYPE_TCP         = 3,    /* TCP/IP */
  50         NVMF_TRTYPE_LOOP        = 254,  /* Reserved for host usage */
  51         NVMF_TRTYPE_MAX,
  52 };
  53
  54 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
  55 enum {
  56         NVMF_TREQ_NOT_SPECIFIED = 0,            /* Not specified */
  57         NVMF_TREQ_REQUIRED      = 1,            /* Required */
  58         NVMF_TREQ_NOT_REQUIRED  = 2,            /* Not Required */
  59 #define NVME_TREQ_SECURE_CHANNEL_MASK \
  60         (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
  61
  62         NVMF_TREQ_DISABLE_SQFLOW = (1 << 2),    /* Supports SQ flow control disable */
  63 };
  64
  65 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  66  * RDMA_QPTYPE field
  67  */
  68 enum {
  69         NVMF_RDMA_QPTYPE_CONNECTED      = 1, /* Reliable Connected */
  70         NVMF_RDMA_QPTYPE_DATAGRAM       = 2, /* Reliable Datagram */
  71 };
  72
  73 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  74  * RDMA_QPTYPE field
  75  */
  76 enum {
  77         NVMF_RDMA_PRTYPE_NOT_SPECIFIED  = 1, /* No Provider Specified */
  78         NVMF_RDMA_PRTYPE_IB             = 2, /* InfiniBand */
  79         NVMF_RDMA_PRTYPE_ROCE           = 3, /* InfiniBand RoCE */
  80         NVMF_RDMA_PRTYPE_ROCEV2         = 4, /* InfiniBand RoCEV2 */
  81         NVMF_RDMA_PRTYPE_IWARP          = 5, /* IWARP */
  82 };
  83
  84 /* RDMA Connection Management Service Type codes for Discovery Log Page
  85  * entry TSAS RDMA_CMS field
  86  */
  87 enum {
  88         NVMF_RDMA_CMS_RDMA_CM   = 1, /* Sockets based endpoint addressing */
  89 };
  90
  91 #define NVME_AQ_DEPTH           32
  92 #define NVME_NR_AEN_COMMANDS    1
  93 #define NVME_AQ_BLK_MQ_DEPTH    (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
  94
  95 /*
  96  * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
  97  * NVM-Express 1.2 specification, section 4.1.2.
  98  */
  99 #define NVME_AQ_MQ_TAG_DEPTH    (NVME_AQ_BLK_MQ_DEPTH - 1)
 100
 101 enum {
 102         NVME_REG_CAP    = 0x0000,       /* Controller Capabilities */
 103         NVME_REG_VS     = 0x0008,       /* Version */
 104         NVME_REG_INTMS  = 0x000c,       /* Interrupt Mask Set */
 105         NVME_REG_INTMC  = 0x0010,       /* Interrupt Mask Clear */
 106         NVME_REG_CC     = 0x0014,       /* Controller Configuration */
 107         NVME_REG_CSTS   = 0x001c,       /* Controller Status */
 108         NVME_REG_NSSR   = 0x0020,       /* NVM Subsystem Reset */
 109         NVME_REG_AQA    = 0x0024,       /* Admin Queue Attributes */
 110         NVME_REG_ASQ    = 0x0028,       /* Admin SQ Base Address */
 111         NVME_REG_ACQ    = 0x0030,       /* Admin CQ Base Address */
 112         NVME_REG_CMBLOC = 0x0038,       /* Controller Memory Buffer Location */
 113         NVME_REG_CMBSZ  = 0x003c,       /* Controller Memory Buffer Size */
 114         NVME_REG_BPINFO = 0x0040,       /* Boot Partition Information */
 115         NVME_REG_BPRSEL = 0x0044,       /* Boot Partition Read Select */
 116         NVME_REG_BPMBL  = 0x0048,       /* Boot Partition Memory Buffer
 117                                          * Location
 118                                          */
 119         NVME_REG_CMBMSC = 0x0050,       /* Controller Memory Buffer Memory
 120                                          * Space Control
 121                                          */
 122         NVME_REG_PMRCAP = 0x0e00,       /* Persistent Memory Capabilities */
 123         NVME_REG_PMRCTL = 0x0e04,       /* Persistent Memory Region Control */
 124         NVME_REG_PMRSTS = 0x0e08,       /* Persistent Memory Region Status */
 125         NVME_REG_PMREBS = 0x0e0c,       /* Persistent Memory Region Elasticity
 126                                          * Buffer Size
 127                                          */
 128         NVME_REG_PMRSWTP = 0x0e10,      /* Persistent Memory Region Sustained
 129                                          * Write Throughput
 130                                          */
 131         NVME_REG_DBS    = 0x1000,       /* SQ 0 Tail Doorbell */
 132 };
 133
 134 #define NVME_CAP_MQES(cap)      ((cap) & 0xffff)
 135 #define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
 136 #define NVME_CAP_STRIDE(cap)    (((cap) >> 32) & 0xf)
 137 #define NVME_CAP_NSSRC(cap)     (((cap) >> 36) & 0x1)
 138 #define NVME_CAP_CSS(cap)       (((cap) >> 37) & 0xff)
 139 #define NVME_CAP_MPSMIN(cap)    (((cap) >> 48) & 0xf)
 140 #define NVME_CAP_MPSMAX(cap)    (((cap) >> 52) & 0xf)
 141 #define NVME_CAP_CMBS(cap)      (((cap) >> 57) & 0x1)
 142
 143 #define NVME_CMB_BIR(cmbloc)    ((cmbloc) & 0x7)
 144 #define NVME_CMB_OFST(cmbloc)   (((cmbloc) >> 12) & 0xfffff)
 145
 146 enum {
 147         NVME_CMBSZ_SQS          = 1 << 0,
 148         NVME_CMBSZ_CQS          = 1 << 1,
 149         NVME_CMBSZ_LISTS        = 1 << 2,
 150         NVME_CMBSZ_RDS          = 1 << 3,
 151         NVME_CMBSZ_WDS          = 1 << 4,
 152
 153         NVME_CMBSZ_SZ_SHIFT     = 12,
 154         NVME_CMBSZ_SZ_MASK      = 0xfffff,
 155
 156         NVME_CMBSZ_SZU_SHIFT    = 8,
 157         NVME_CMBSZ_SZU_MASK     = 0xf,
 158 };
 159
 160 /*
 161  * Submission and Completion Queue Entry Sizes for the NVM command set.
 162  * (In bytes and specified as a power of two (2^n)).
 163  */
 164 #define NVME_ADM_SQES       6
 165 #define NVME_NVM_IOSQES         6
 166 #define NVME_NVM_IOCQES         4
 167
 168 enum {
 169         NVME_CC_ENABLE          = 1 << 0,
 170         NVME_CC_EN_SHIFT        = 0,
 171         NVME_CC_CSS_SHIFT       = 4,
 172         NVME_CC_MPS_SHIFT       = 7,
 173         NVME_CC_AMS_SHIFT       = 11,
 174         NVME_CC_SHN_SHIFT       = 14,
 175         NVME_CC_IOSQES_SHIFT    = 16,
 176         NVME_CC_IOCQES_SHIFT    = 20,
 177         NVME_CC_CSS_NVM         = 0 << NVME_CC_CSS_SHIFT,
 178         NVME_CC_CSS_CSI         = 6 << NVME_CC_CSS_SHIFT,
 179         NVME_CC_CSS_MASK        = 7 << NVME_CC_CSS_SHIFT,
 180         NVME_CC_AMS_RR          = 0 << NVME_CC_AMS_SHIFT,
 181         NVME_CC_AMS_WRRU        = 1 << NVME_CC_AMS_SHIFT,
 182         NVME_CC_AMS_VS          = 7 << NVME_CC_AMS_SHIFT,
 183         NVME_CC_SHN_NONE        = 0 << NVME_CC_SHN_SHIFT,
 184         NVME_CC_SHN_NORMAL      = 1 << NVME_CC_SHN_SHIFT,
 185         NVME_CC_SHN_ABRUPT      = 2 << NVME_CC_SHN_SHIFT,
 186         NVME_CC_SHN_MASK        = 3 << NVME_CC_SHN_SHIFT,
 187         NVME_CC_IOSQES          = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
 188         NVME_CC_IOCQES          = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
 189         NVME_CAP_CSS_NVM        = 1 << 0,
 190         NVME_CAP_CSS_CSI        = 1 << 6,
 191         NVME_CSTS_RDY           = 1 << 0,
 192         NVME_CSTS_CFS           = 1 << 1,
 193         NVME_CSTS_NSSRO         = 1 << 4,
 194         NVME_CSTS_PP            = 1 << 5,
 195         NVME_CSTS_SHST_NORMAL   = 0 << 2,
 196         NVME_CSTS_SHST_OCCUR    = 1 << 2,
 197         NVME_CSTS_SHST_CMPLT    = 2 << 2,
 198         NVME_CSTS_SHST_MASK     = 3 << 2,
 199         NVME_CMBMSC_CRE         = 1 << 0,
 200         NVME_CMBMSC_CMSE        = 1 << 1,
 201 };
 202
 203 struct nvme_id_power_state {
 204         __le16                  max_power;      /* centiwatts */
 205         __u8                    rsvd2;
 206         __u8                    flags;
 207         __le32                  entry_lat;      /* microseconds */
 208         __le32                  exit_lat;       /* microseconds */
 209         __u8                    read_tput;
 210         __u8                    read_lat;
 211         __u8                    write_tput;
 212         __u8                    write_lat;
 213         __le16                  idle_power;
 214         __u8                    idle_scale;
 215         __u8                    rsvd19;
 216         __le16                  active_power;
 217         __u8                    active_work_scale;
 218         __u8                    rsvd23[9];
 219 };
 220
 221 enum {
 222         NVME_PS_FLAGS_MAX_POWER_SCALE   = 1 << 0,
 223         NVME_PS_FLAGS_NON_OP_STATE      = 1 << 1,
 224 };
 225
 226 enum nvme_ctrl_attr {
 227         NVME_CTRL_ATTR_HID_128_BIT      = (1 << 0),
 228         NVME_CTRL_ATTR_TBKAS            = (1 << 6),
 229 };
 230
 231 struct nvme_id_ctrl {
 232         __le16                  vid;
 233         __le16                  ssvid;
 234         char                    sn[20];
 235         char                    mn[40];
 236         char                    fr[8];
 237         __u8                    rab;
 238         __u8                    ieee[3];
 239         __u8                    cmic;
 240         __u8                    mdts;
 241         __le16                  cntlid;
 242         __le32                  ver;
 243         __le32                  rtd3r;
 244         __le32                  rtd3e;
 245         __le32                  oaes;
 246         __le32                  ctratt;
 247         __u8                    rsvd100[28];
 248         __le16                  crdt1;
 249         __le16                  crdt2;
 250         __le16                  crdt3;
 251         __u8                    rsvd134[122];
 252         __le16                  oacs;
 253         __u8                    acl;
 254         __u8                    aerl;
 255         __u8                    frmw;
 256         __u8                    lpa;
 257         __u8                    elpe;
 258         __u8                    npss;
 259         __u8                    avscc;
 260         __u8                    apsta;
 261         __le16                  wctemp;
 262         __le16                  cctemp;
 263         __le16                  mtfa;
 264         __le32                  hmpre;
 265         __le32                  hmmin;
 266         __u8                    tnvmcap[16];
 267         __u8                    unvmcap[16];
 268         __le32                  rpmbs;
 269         __le16                  edstt;
 270         __u8                    dsto;
 271         __u8                    fwug;
 272         __le16                  kas;
 273         __le16                  hctma;
 274         __le16                  mntmt;
 275         __le16                  mxtmt;
 276         __le32                  sanicap;
 277         __le32                  hmminds;
 278         __le16                  hmmaxd;
 279         __u8                    rsvd338[4];
 280         __u8                    anatt;
 281         __u8                    anacap;
 282         __le32                  anagrpmax;
 283         __le32                  nanagrpid;
 284         __u8                    rsvd352[160];
 285         __u8                    sqes;
 286         __u8                    cqes;
 287         __le16                  maxcmd;
 288         __le32                  nn;
 289         __le16                  oncs;
 290         __le16                  fuses;
 291         __u8                    fna;
 292         __u8                    vwc;
 293         __le16                  awun;
 294         __le16                  awupf;
 295         __u8                    nvscc;
 296         __u8                    nwpc;
 297         __le16                  acwu;
 298         __u8                    rsvd534[2];
 299         __le32                  sgls;
 300         __le32                  mnan;
 301         __u8                    rsvd544[224];
 302         char                    subnqn[256];
 303         __u8                    rsvd1024[768];
 304         __le32                  ioccsz;
 305         __le32                  iorcsz;
 306         __le16                  icdoff;
 307         __u8                    ctrattr;
 308         __u8                    msdbd;
 309         __u8                    rsvd1804[244];
 310         struct nvme_id_power_state      psd[32];
 311         __u8                    vs[1024];
 312 };
 313
 314 enum {
 315         NVME_CTRL_CMIC_MULTI_CTRL               = 1 << 1,
 316         NVME_CTRL_CMIC_ANA                      = 1 << 3,
 317         NVME_CTRL_ONCS_COMPARE                  = 1 << 0,
 318         NVME_CTRL_ONCS_WRITE_UNCORRECTABLE      = 1 << 1,
 319         NVME_CTRL_ONCS_DSM                      = 1 << 2,
 320         NVME_CTRL_ONCS_WRITE_ZEROES             = 1 << 3,
 321         NVME_CTRL_ONCS_RESERVATIONS             = 1 << 5,
 322         NVME_CTRL_ONCS_TIMESTAMP                = 1 << 6,
 323         NVME_CTRL_VWC_PRESENT                   = 1 << 0,
 324         NVME_CTRL_OACS_SEC_SUPP                 = 1 << 0,
 325         NVME_CTRL_OACS_DIRECTIVES               = 1 << 5,
 326         NVME_CTRL_OACS_DBBUF_SUPP               = 1 << 8,
 327         NVME_CTRL_LPA_CMD_EFFECTS_LOG           = 1 << 1,
 328         NVME_CTRL_CTRATT_128_ID                 = 1 << 0,
 329         NVME_CTRL_CTRATT_NON_OP_PSP             = 1 << 1,
 330         NVME_CTRL_CTRATT_NVM_SETS               = 1 << 2,
 331         NVME_CTRL_CTRATT_READ_RECV_LVLS         = 1 << 3,
 332         NVME_CTRL_CTRATT_ENDURANCE_GROUPS       = 1 << 4,
 333         NVME_CTRL_CTRATT_PREDICTABLE_LAT        = 1 << 5,
 334         NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY  = 1 << 7,
 335         NVME_CTRL_CTRATT_UUID_LIST              = 1 << 9,
 336 };
 337
 338 struct nvme_lbaf {
 339         __le16                  ms;
 340         __u8                    ds;
 341         __u8                    rp;
 342 };
 343
 344 struct nvme_id_ns {
 345         __le64                  nsze;
 346         __le64                  ncap;
 347         __le64                  nuse;
 348         __u8                    nsfeat;
 349         __u8                    nlbaf;
 350         __u8                    flbas;
 351         __u8                    mc;
 352         __u8                    dpc;
 353         __u8                    dps;
 354         __u8                    nmic;
 355         __u8                    rescap;
 356         __u8                    fpi;
 357         __u8                    dlfeat;
 358         __le16                  nawun;
 359         __le16                  nawupf;
 360         __le16                  nacwu;
 361         __le16                  nabsn;
 362         __le16                  nabo;
 363         __le16                  nabspf;
 364         __le16                  noiob;
 365         __u8                    nvmcap[16];
 366         __le16                  npwg;
 367         __le16                  npwa;
 368         __le16                  npdg;
 369         __le16                  npda;
 370         __le16                  nows;
 371         __u8                    rsvd74[18];
 372         __le32                  anagrpid;
 373         __u8                    rsvd96[3];
 374         __u8                    nsattr;
 375         __le16                  nvmsetid;
 376         __le16                  endgid;
 377         __u8                    nguid[16];
 378         __u8                    eui64[8];
 379         struct nvme_lbaf        lbaf[16];
 380         __u8                    rsvd192[192];
 381         __u8                    vs[3712];
 382 };
 383
 384 struct nvme_zns_lbafe {
 385         __le64                  zsze;
 386         __u8                    zdes;
 387         __u8                    rsvd9[7];
 388 };
 389
 390 struct nvme_id_ns_zns {
 391         __le16                  zoc;
 392         __le16                  ozcs;
 393         __le32                  mar;
 394         __le32                  mor;
 395         __le32                  rrl;
 396         __le32                  frl;
 397         __u8                    rsvd20[2796];
 398         struct nvme_zns_lbafe   lbafe[16];
 399         __u8                    rsvd3072[768];
 400         __u8                    vs[256];
 401 };
 402
 403 struct nvme_id_ctrl_zns {
 404         __u8    zasl;
 405         __u8    rsvd1[4095];
 406 };
 407
 408 struct nvme_id_ctrl_nvm {
 409         __u8    vsl;
 410         __u8    wzsl;
 411         __u8    wusl;
 412         __u8    dmrl;
 413         __le32  dmrsl;
 414         __le64  dmsl;
 415         __u8    rsvd16[4080];
 416 };
 417
 418 enum {
 419         NVME_ID_CNS_NS                  = 0x00,
 420         NVME_ID_CNS_CTRL                = 0x01,
 421         NVME_ID_CNS_NS_ACTIVE_LIST      = 0x02,
 422         NVME_ID_CNS_NS_DESC_LIST        = 0x03,
 423         NVME_ID_CNS_CS_NS               = 0x05,
 424         NVME_ID_CNS_CS_CTRL             = 0x06,
 425         NVME_ID_CNS_NS_PRESENT_LIST     = 0x10,
 426         NVME_ID_CNS_NS_PRESENT          = 0x11,
 427         NVME_ID_CNS_CTRL_NS_LIST        = 0x12,
 428         NVME_ID_CNS_CTRL_LIST           = 0x13,
 429         NVME_ID_CNS_SCNDRY_CTRL_LIST    = 0x15,
 430         NVME_ID_CNS_NS_GRANULARITY      = 0x16,
 431         NVME_ID_CNS_UUID_LIST           = 0x17,
 432 };
 433
 434 enum {
 435         NVME_CSI_NVM                    = 0,
 436         NVME_CSI_ZNS                    = 2,
 437 };
 438
 439 enum {
 440         NVME_DIR_IDENTIFY               = 0x00,
 441         NVME_DIR_STREAMS                = 0x01,
 442         NVME_DIR_SND_ID_OP_ENABLE       = 0x01,
 443         NVME_DIR_SND_ST_OP_REL_ID       = 0x01,
 444         NVME_DIR_SND_ST_OP_REL_RSC      = 0x02,
 445         NVME_DIR_RCV_ID_OP_PARAM        = 0x01,
 446         NVME_DIR_RCV_ST_OP_PARAM        = 0x01,
 447         NVME_DIR_RCV_ST_OP_STATUS       = 0x02,
 448         NVME_DIR_RCV_ST_OP_RESOURCE     = 0x03,
 449         NVME_DIR_ENDIR                  = 0x01,
 450 };
 451
 452 enum {
 453         NVME_NS_FEAT_THIN       = 1 << 0,
 454         NVME_NS_FEAT_ATOMICS    = 1 << 1,
 455         NVME_NS_FEAT_IO_OPT     = 1 << 4,
 456         NVME_NS_ATTR_RO         = 1 << 0,
 457         NVME_NS_FLBAS_LBA_MASK  = 0xf,
 458         NVME_NS_FLBAS_META_EXT  = 0x10,
 459         NVME_NS_NMIC_SHARED     = 1 << 0,
 460         NVME_LBAF_RP_BEST       = 0,
 461         NVME_LBAF_RP_BETTER     = 1,
 462         NVME_LBAF_RP_GOOD       = 2,
 463         NVME_LBAF_RP_DEGRADED   = 3,
 464         NVME_NS_DPC_PI_LAST     = 1 << 4,
 465         NVME_NS_DPC_PI_FIRST    = 1 << 3,
 466         NVME_NS_DPC_PI_TYPE3    = 1 << 2,
 467         NVME_NS_DPC_PI_TYPE2    = 1 << 1,
 468         NVME_NS_DPC_PI_TYPE1    = 1 << 0,
 469         NVME_NS_DPS_PI_FIRST    = 1 << 3,
 470         NVME_NS_DPS_PI_MASK     = 0x7,
 471         NVME_NS_DPS_PI_TYPE1    = 1,
 472         NVME_NS_DPS_PI_TYPE2    = 2,
 473         NVME_NS_DPS_PI_TYPE3    = 3,
 474 };
 475
 476 /* Identify Namespace Metadata Capabilities (MC): */
 477 enum {
 478         NVME_MC_EXTENDED_LBA    = (1 << 0),
 479         NVME_MC_METADATA_PTR    = (1 << 1),
 480 };
 481
 482 struct nvme_ns_id_desc {
 483         __u8 nidt;
 484         __u8 nidl;
 485         __le16 reserved;
 486 };
 487
 488 #define NVME_NIDT_EUI64_LEN     8
 489 #define NVME_NIDT_NGUID_LEN     16
 490 #define NVME_NIDT_UUID_LEN      16
 491 #define NVME_NIDT_CSI_LEN       1
 492
 493 enum {
 494         NVME_NIDT_EUI64         = 0x01,
 495         NVME_NIDT_NGUID         = 0x02,
 496         NVME_NIDT_UUID          = 0x03,
 497         NVME_NIDT_CSI           = 0x04,
 498 };
 499
 500 struct nvme_smart_log {
 501         __u8                    critical_warning;
 502         __u8                    temperature[2];
 503         __u8                    avail_spare;
 504         __u8                    spare_thresh;
 505         __u8                    percent_used;
 506         __u8                    endu_grp_crit_warn_sumry;
 507         __u8                    rsvd7[25];
 508         __u8                    data_units_read[16];
 509         __u8                    data_units_written[16];
 510         __u8                    host_reads[16];
 511         __u8                    host_writes[16];
 512         __u8                    ctrl_busy_time[16];
 513         __u8                    power_cycles[16];
 514         __u8                    power_on_hours[16];
 515         __u8                    unsafe_shutdowns[16];
 516         __u8                    media_errors[16];
 517         __u8                    num_err_log_entries[16];
 518         __le32                  warning_temp_time;
 519         __le32                  critical_comp_time;
 520         __le16                  temp_sensor[8];
 521         __le32                  thm_temp1_trans_count;
 522         __le32                  thm_temp2_trans_count;
 523         __le32                  thm_temp1_total_time;
 524         __le32                  thm_temp2_total_time;
 525         __u8                    rsvd232[280];
 526 };
 527
 528 struct nvme_fw_slot_info_log {
 529         __u8                    afi;
 530         __u8                    rsvd1[7];
 531         __le64                  frs[7];
 532         __u8                    rsvd64[448];
 533 };
 534
 535 enum {
 536         NVME_CMD_EFFECTS_CSUPP          = 1 << 0,
 537         NVME_CMD_EFFECTS_LBCC           = 1 << 1,
 538         NVME_CMD_EFFECTS_NCC            = 1 << 2,
 539         NVME_CMD_EFFECTS_NIC            = 1 << 3,
 540         NVME_CMD_EFFECTS_CCC            = 1 << 4,
 541         NVME_CMD_EFFECTS_CSE_MASK       = 3 << 16,
 542         NVME_CMD_EFFECTS_UUID_SEL       = 1 << 19,
 543 };
 544
 545 struct nvme_effects_log {
 546         __le32 acs[256];
 547         __le32 iocs[256];
 548         __u8   resv[2048];
 549 };
 550
 551 enum nvme_ana_state {
 552         NVME_ANA_OPTIMIZED              = 0x01,
 553         NVME_ANA_NONOPTIMIZED           = 0x02,
 554         NVME_ANA_INACCESSIBLE           = 0x03,
 555         NVME_ANA_PERSISTENT_LOSS        = 0x04,
 556         NVME_ANA_CHANGE                 = 0x0f,
 557 };
 558
 559 struct nvme_ana_group_desc {
 560         __le32  grpid;
 561         __le32  nnsids;
 562         __le64  chgcnt;
 563         __u8    state;
 564         __u8    rsvd17[15];
 565         __le32  nsids[];
 566 };
 567
 568 /* flag for the log specific field of the ANA log */
 569 #define NVME_ANA_LOG_RGO        (1 << 0)
 570
 571 struct nvme_ana_rsp_hdr {
 572         __le64  chgcnt;
 573         __le16  ngrps;
 574         __le16  rsvd10[3];
 575 };
 576
 577 struct nvme_zone_descriptor {
 578         __u8            zt;
 579         __u8            zs;
 580         __u8            za;
 581         __u8            rsvd3[5];
 582         __le64          zcap;
 583         __le64          zslba;
 584         __le64          wp;
 585         __u8            rsvd32[32];
 586 };
 587
 588 enum {
 589         NVME_ZONE_TYPE_SEQWRITE_REQ     = 0x2,
 590 };
 591
 592 struct nvme_zone_report {
 593         __le64          nr_zones;
 594         __u8            resv8[56];
 595         struct nvme_zone_descriptor entries[];
 596 };
 597
 598 enum {
 599         NVME_SMART_CRIT_SPARE           = 1 << 0,
 600         NVME_SMART_CRIT_TEMPERATURE     = 1 << 1,
 601         NVME_SMART_CRIT_RELIABILITY     = 1 << 2,
 602         NVME_SMART_CRIT_MEDIA           = 1 << 3,
 603         NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
 604 };
 605
 606 enum {
 607         NVME_AER_ERROR                  = 0,
 608         NVME_AER_SMART                  = 1,
 609         NVME_AER_NOTICE                 = 2,
 610         NVME_AER_CSS                    = 6,
 611         NVME_AER_VS                     = 7,
 612 };
 613
 614 enum {
 615         NVME_AER_NOTICE_NS_CHANGED      = 0x00,
 616         NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
 617         NVME_AER_NOTICE_ANA             = 0x03,
 618         NVME_AER_NOTICE_DISC_CHANGED    = 0xf0,
 619 };
 620
 621 enum {
 622         NVME_AEN_BIT_NS_ATTR            = 8,
 623         NVME_AEN_BIT_FW_ACT             = 9,
 624         NVME_AEN_BIT_ANA_CHANGE         = 11,
 625         NVME_AEN_BIT_DISC_CHANGE        = 31,
 626 };
 627
 628 enum {
 629         NVME_AEN_CFG_NS_ATTR            = 1 << NVME_AEN_BIT_NS_ATTR,
 630         NVME_AEN_CFG_FW_ACT             = 1 << NVME_AEN_BIT_FW_ACT,
 631         NVME_AEN_CFG_ANA_CHANGE         = 1 << NVME_AEN_BIT_ANA_CHANGE,
 632         NVME_AEN_CFG_DISC_CHANGE        = 1 << NVME_AEN_BIT_DISC_CHANGE,
 633 };
 634
 635 struct nvme_lba_range_type {
 636         __u8                    type;
 637         __u8                    attributes;
 638         __u8                    rsvd2[14];
 639         __le64                  slba;
 640         __le64                  nlb;
 641         __u8                    guid[16];
 642         __u8                    rsvd48[16];
 643 };
 644
 645 enum {
 646         NVME_LBART_TYPE_FS      = 0x01,
 647         NVME_LBART_TYPE_RAID    = 0x02,
 648         NVME_LBART_TYPE_CACHE   = 0x03,
 649         NVME_LBART_TYPE_SWAP    = 0x04,
 650
 651         NVME_LBART_ATTRIB_TEMP  = 1 << 0,
 652         NVME_LBART_ATTRIB_HIDE  = 1 << 1,
 653 };
 654
 655 struct nvme_reservation_status {
 656         __le32  gen;
 657         __u8    rtype;
 658         __u8    regctl[2];
 659         __u8    resv5[2];
 660         __u8    ptpls;
 661         __u8    resv10[13];
 662         struct {
 663                 __le16  cntlid;
 664                 __u8    rcsts;
 665                 __u8    resv3[5];
 666                 __le64  hostid;
 667                 __le64  rkey;
 668         } regctl_ds[];
 669 };
 670
 671 enum nvme_async_event_type {
 672         NVME_AER_TYPE_ERROR     = 0,
 673         NVME_AER_TYPE_SMART     = 1,
 674         NVME_AER_TYPE_NOTICE    = 2,
 675 };
 676
 677 /* I/O commands */
 678
 679 enum nvme_opcode {
 680         nvme_cmd_flush          = 0x00,
 681         nvme_cmd_write          = 0x01,
 682         nvme_cmd_read           = 0x02,
 683         nvme_cmd_write_uncor    = 0x04,
 684         nvme_cmd_compare        = 0x05,
 685         nvme_cmd_write_zeroes   = 0x08,
 686         nvme_cmd_dsm            = 0x09,
 687         nvme_cmd_verify         = 0x0c,
 688         nvme_cmd_resv_register  = 0x0d,
 689         nvme_cmd_resv_report    = 0x0e,
 690         nvme_cmd_resv_acquire   = 0x11,
 691         nvme_cmd_resv_release   = 0x15,
 692         nvme_cmd_zone_mgmt_send = 0x79,
 693         nvme_cmd_zone_mgmt_recv = 0x7a,
 694         nvme_cmd_zone_append    = 0x7d,
 695 };
 696
 697 #define nvme_opcode_name(opcode)        { opcode, #opcode }
 698 #define show_nvm_opcode_name(val)                               \
 699         __print_symbolic(val,                                   \
 700                 nvme_opcode_name(nvme_cmd_flush),               \
 701                 nvme_opcode_name(nvme_cmd_write),               \
 702                 nvme_opcode_name(nvme_cmd_read),                \
 703                 nvme_opcode_name(nvme_cmd_write_uncor),         \
 704                 nvme_opcode_name(nvme_cmd_compare),             \
 705                 nvme_opcode_name(nvme_cmd_write_zeroes),        \
 706                 nvme_opcode_name(nvme_cmd_dsm),                 \
 707                 nvme_opcode_name(nvme_cmd_resv_register),       \
 708                 nvme_opcode_name(nvme_cmd_resv_report),         \
 709                 nvme_opcode_name(nvme_cmd_resv_acquire),        \
 710                 nvme_opcode_name(nvme_cmd_resv_release),        \
 711                 nvme_opcode_name(nvme_cmd_zone_mgmt_send),      \
 712                 nvme_opcode_name(nvme_cmd_zone_mgmt_recv),      \
 713                 nvme_opcode_name(nvme_cmd_zone_append))
 714
 715
 716
 717 /*
 718  * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
 719  *
 720  * @NVME_SGL_FMT_ADDRESS:     absolute address of the data block
 721  * @NVME_SGL_FMT_OFFSET:      relative offset of the in-capsule data block
 722  * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
 723  * @NVME_SGL_FMT_INVALIDATE:  RDMA transport specific remote invalidation
 724  *                            request subtype
 725  */
 726 enum {
 727         NVME_SGL_FMT_ADDRESS            = 0x00,
 728         NVME_SGL_FMT_OFFSET             = 0x01,
 729         NVME_SGL_FMT_TRANSPORT_A        = 0x0A,
 730         NVME_SGL_FMT_INVALIDATE         = 0x0f,
 731 };
 732
 733 /*
 734  * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
 735  *
 736  * For struct nvme_sgl_desc:
 737  *   @NVME_SGL_FMT_DATA_DESC:           data block descriptor
 738  *   @NVME_SGL_FMT_SEG_DESC:            sgl segment descriptor
 739  *   @NVME_SGL_FMT_LAST_SEG_DESC:       last sgl segment descriptor
 740  *
 741  * For struct nvme_keyed_sgl_desc:
 742  *   @NVME_KEY_SGL_FMT_DATA_DESC:       keyed data block descriptor
 743  *
 744  * Transport-specific SGL types:
 745  *   @NVME_TRANSPORT_SGL_DATA_DESC:     Transport SGL data dlock descriptor
 746  */
 747 enum {
 748         NVME_SGL_FMT_DATA_DESC          = 0x00,
 749         NVME_SGL_FMT_SEG_DESC           = 0x02,
 750         NVME_SGL_FMT_LAST_SEG_DESC      = 0x03,
 751         NVME_KEY_SGL_FMT_DATA_DESC      = 0x04,
 752         NVME_TRANSPORT_SGL_DATA_DESC    = 0x05,
 753 };
 754
 755 struct nvme_sgl_desc {
 756         __le64  addr;
 757         __le32  length;
 758         __u8    rsvd[3];
 759         __u8    type;
 760 };
 761
 762 struct nvme_keyed_sgl_desc {
 763         __le64  addr;
 764         __u8    length[3];
 765         __u8    key[4];
 766         __u8    type;
 767 };
 768
 769 union nvme_data_ptr {
 770         struct {
 771                 __le64  prp1;
 772                 __le64  prp2;
 773         };
 774         struct nvme_sgl_desc    sgl;
 775         struct nvme_keyed_sgl_desc ksgl;
 776 };
 777
 778 /*
 779  * Lowest two bits of our flags field (FUSE field in the spec):
 780  *
 781  * @NVME_CMD_FUSE_FIRST:   Fused Operation, first command
 782  * @NVME_CMD_FUSE_SECOND:  Fused Operation, second command
 783  *
 784  * Highest two bits in our flags field (PSDT field in the spec):
 785  *
 786  * @NVME_CMD_PSDT_SGL_METABUF:  Use SGLS for this transfer,
 787  *      If used, MPTR contains addr of single physical buffer (byte aligned).
 788  * @NVME_CMD_PSDT_SGL_METASEG:  Use SGLS for this transfer,
 789  *      If used, MPTR contains an address of an SGL segment containing
 790  *      exactly 1 SGL descriptor (qword aligned).
 791  */
 792 enum {
 793         NVME_CMD_FUSE_FIRST     = (1 << 0),
 794         NVME_CMD_FUSE_SECOND    = (1 << 1),
 795
 796         NVME_CMD_SGL_METABUF    = (1 << 6),
 797         NVME_CMD_SGL_METASEG    = (1 << 7),
 798         NVME_CMD_SGL_ALL        = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
 799 };
 800
 801 struct nvme_common_command {
 802         __u8                    opcode;
 803         __u8                    flags;
 804         __u16                   command_id;
 805         __le32                  nsid;
 806         __le32                  cdw2[2];
 807         __le64                  metadata;
 808         union nvme_data_ptr     dptr;
 809         __le32                  cdw10;
 810         __le32                  cdw11;
 811         __le32                  cdw12;
 812         __le32                  cdw13;
 813         __le32                  cdw14;
 814         __le32                  cdw15;
 815 };
 816
 817 struct nvme_rw_command {
 818         __u8                    opcode;
 819         __u8                    flags;
 820         __u16                   command_id;
 821         __le32                  nsid;
 822         __u64                   rsvd2;
 823         __le64                  metadata;
 824         union nvme_data_ptr     dptr;
 825         __le64                  slba;
 826         __le16                  length;
 827         __le16                  control;
 828         __le32                  dsmgmt;
 829         __le32                  reftag;
 830         __le16                  apptag;
 831         __le16                  appmask;
 832 };
 833
 834 enum {
 835         NVME_RW_LR                      = 1 << 15,
 836         NVME_RW_FUA                     = 1 << 14,
 837         NVME_RW_APPEND_PIREMAP          = 1 << 9,
 838         NVME_RW_DSM_FREQ_UNSPEC         = 0,
 839         NVME_RW_DSM_FREQ_TYPICAL        = 1,
 840         NVME_RW_DSM_FREQ_RARE           = 2,
 841         NVME_RW_DSM_FREQ_READS          = 3,
 842         NVME_RW_DSM_FREQ_WRITES         = 4,
 843         NVME_RW_DSM_FREQ_RW             = 5,
 844         NVME_RW_DSM_FREQ_ONCE           = 6,
 845         NVME_RW_DSM_FREQ_PREFETCH       = 7,
 846         NVME_RW_DSM_FREQ_TEMP           = 8,
 847         NVME_RW_DSM_LATENCY_NONE        = 0 << 4,
 848         NVME_RW_DSM_LATENCY_IDLE        = 1 << 4,
 849         NVME_RW_DSM_LATENCY_NORM        = 2 << 4,
 850         NVME_RW_DSM_LATENCY_LOW         = 3 << 4,
 851         NVME_RW_DSM_SEQ_REQ             = 1 << 6,
 852         NVME_RW_DSM_COMPRESSED          = 1 << 7,
 853         NVME_RW_PRINFO_PRCHK_REF        = 1 << 10,
 854         NVME_RW_PRINFO_PRCHK_APP        = 1 << 11,
 855         NVME_RW_PRINFO_PRCHK_GUARD      = 1 << 12,
 856         NVME_RW_PRINFO_PRACT            = 1 << 13,
 857         NVME_RW_DTYPE_STREAMS           = 1 << 4,
 858 };
 859
 860 struct nvme_dsm_cmd {
 861         __u8                    opcode;
 862         __u8                    flags;
 863         __u16                   command_id;
 864         __le32                  nsid;
 865         __u64                   rsvd2[2];
 866         union nvme_data_ptr     dptr;
 867         __le32                  nr;
 868         __le32                  attributes;
 869         __u32                   rsvd12[4];
 870 };
 871
 872 enum {
 873         NVME_DSMGMT_IDR         = 1 << 0,
 874         NVME_DSMGMT_IDW         = 1 << 1,
 875         NVME_DSMGMT_AD          = 1 << 2,
 876 };
 877
 878 #define NVME_DSM_MAX_RANGES     256
 879
 880 struct nvme_dsm_range {
 881         __le32                  cattr;
 882         __le32                  nlb;
 883         __le64                  slba;
 884 };
 885
 886 struct nvme_write_zeroes_cmd {
 887         __u8                    opcode;
 888         __u8                    flags;
 889         __u16                   command_id;
 890         __le32                  nsid;
 891         __u64                   rsvd2;
 892         __le64                  metadata;
 893         union nvme_data_ptr     dptr;
 894         __le64                  slba;
 895         __le16                  length;
 896         __le16                  control;
 897         __le32                  dsmgmt;
 898         __le32                  reftag;
 899         __le16                  apptag;
 900         __le16                  appmask;
 901 };
 902
 903 enum nvme_zone_mgmt_action {
 904         NVME_ZONE_CLOSE         = 0x1,
 905         NVME_ZONE_FINISH        = 0x2,
 906         NVME_ZONE_OPEN          = 0x3,
 907         NVME_ZONE_RESET         = 0x4,
 908         NVME_ZONE_OFFLINE       = 0x5,
 909         NVME_ZONE_SET_DESC_EXT  = 0x10,
 910 };
 911
 912 struct nvme_zone_mgmt_send_cmd {
 913         __u8                    opcode;
 914         __u8                    flags;
 915         __u16                   command_id;
 916         __le32                  nsid;
 917         __le32                  cdw2[2];
 918         __le64                  metadata;
 919         union nvme_data_ptr     dptr;
 920         __le64                  slba;
 921         __le32                  cdw12;
 922         __u8                    zsa;
 923         __u8                    select_all;
 924         __u8                    rsvd13[2];
 925         __le32                  cdw14[2];
 926 };
 927
 928 struct nvme_zone_mgmt_recv_cmd {
 929         __u8                    opcode;
 930         __u8                    flags;
 931         __u16                   command_id;
 932         __le32                  nsid;
 933         __le64                  rsvd2[2];
 934         union nvme_data_ptr     dptr;
 935         __le64                  slba;
 936         __le32                  numd;
 937         __u8                    zra;
 938         __u8                    zrasf;
 939         __u8                    pr;
 940         __u8                    rsvd13;
 941         __le32                  cdw14[2];
 942 };
 943
 944 enum {
 945         NVME_ZRA_ZONE_REPORT            = 0,
 946         NVME_ZRASF_ZONE_REPORT_ALL      = 0,
 947         NVME_ZRASF_ZONE_STATE_EMPTY     = 0x01,
 948         NVME_ZRASF_ZONE_STATE_IMP_OPEN  = 0x02,
 949         NVME_ZRASF_ZONE_STATE_EXP_OPEN  = 0x03,
 950         NVME_ZRASF_ZONE_STATE_CLOSED    = 0x04,
 951         NVME_ZRASF_ZONE_STATE_READONLY  = 0x05,
 952         NVME_ZRASF_ZONE_STATE_FULL      = 0x06,
 953         NVME_ZRASF_ZONE_STATE_OFFLINE   = 0x07,
 954         NVME_REPORT_ZONE_PARTIAL        = 1,
 955 };
 956
 957 /* Features */
 958
 959 enum {
 960         NVME_TEMP_THRESH_MASK           = 0xffff,
 961         NVME_TEMP_THRESH_SELECT_SHIFT   = 16,
 962         NVME_TEMP_THRESH_TYPE_UNDER     = 0x100000,
 963 };
 964
 965 struct nvme_feat_auto_pst {
 966         __le64 entries[32];
 967 };
 968
 969 enum {
 970         NVME_HOST_MEM_ENABLE    = (1 << 0),
 971         NVME_HOST_MEM_RETURN    = (1 << 1),
 972 };
 973
 974 struct nvme_feat_host_behavior {
 975         __u8 acre;
 976         __u8 resv1[511];
 977 };
 978
 979 enum {
 980         NVME_ENABLE_ACRE        = 1,
 981 };
 982
 983 /* Admin commands */
 984
 985 enum nvme_admin_opcode {
 986         nvme_admin_delete_sq            = 0x00,
 987         nvme_admin_create_sq            = 0x01,
 988         nvme_admin_get_log_page         = 0x02,
 989         nvme_admin_delete_cq            = 0x04,
 990         nvme_admin_create_cq            = 0x05,
 991         nvme_admin_identify             = 0x06,
 992         nvme_admin_abort_cmd            = 0x08,
 993         nvme_admin_set_features         = 0x09,
 994         nvme_admin_get_features         = 0x0a,
 995         nvme_admin_async_event          = 0x0c,
 996         nvme_admin_ns_mgmt              = 0x0d,
 997         nvme_admin_activate_fw          = 0x10,
 998         nvme_admin_download_fw          = 0x11,
 999         nvme_admin_dev_self_test        = 0x14,
1000         nvme_admin_ns_attach            = 0x15,
1001         nvme_admin_keep_alive           = 0x18,
1002         nvme_admin_directive_send       = 0x19,
1003         nvme_admin_directive_recv       = 0x1a,
1004         nvme_admin_virtual_mgmt         = 0x1c,
1005         nvme_admin_nvme_mi_send         = 0x1d,
1006         nvme_admin_nvme_mi_recv         = 0x1e,
1007         nvme_admin_dbbuf                = 0x7C,
1008         nvme_admin_format_nvm           = 0x80,
1009         nvme_admin_security_send        = 0x81,
1010         nvme_admin_security_recv        = 0x82,
1011         nvme_admin_sanitize_nvm         = 0x84,
1012         nvme_admin_get_lba_status       = 0x86,
1013         nvme_admin_vendor_start         = 0xC0,
1014 };
1015
1016 #define nvme_admin_opcode_name(opcode)  { opcode, #opcode }
1017 #define show_admin_opcode_name(val)                                     \
1018         __print_symbolic(val,                                           \
1019                 nvme_admin_opcode_name(nvme_admin_delete_sq),           \
1020                 nvme_admin_opcode_name(nvme_admin_create_sq),           \
1021                 nvme_admin_opcode_name(nvme_admin_get_log_page),        \
1022                 nvme_admin_opcode_name(nvme_admin_delete_cq),           \
1023                 nvme_admin_opcode_name(nvme_admin_create_cq),           \
1024                 nvme_admin_opcode_name(nvme_admin_identify),            \
1025                 nvme_admin_opcode_name(nvme_admin_abort_cmd),           \
1026                 nvme_admin_opcode_name(nvme_admin_set_features),        \
1027                 nvme_admin_opcode_name(nvme_admin_get_features),        \
1028                 nvme_admin_opcode_name(nvme_admin_async_event),         \
1029                 nvme_admin_opcode_name(nvme_admin_ns_mgmt),             \
1030                 nvme_admin_opcode_name(nvme_admin_activate_fw),         \
1031                 nvme_admin_opcode_name(nvme_admin_download_fw),         \
1032                 nvme_admin_opcode_name(nvme_admin_ns_attach),           \
1033                 nvme_admin_opcode_name(nvme_admin_keep_alive),          \
1034                 nvme_admin_opcode_name(nvme_admin_directive_send),      \
1035                 nvme_admin_opcode_name(nvme_admin_directive_recv),      \
1036                 nvme_admin_opcode_name(nvme_admin_dbbuf),               \
1037                 nvme_admin_opcode_name(nvme_admin_format_nvm),          \
1038                 nvme_admin_opcode_name(nvme_admin_security_send),       \
1039                 nvme_admin_opcode_name(nvme_admin_security_recv),       \
1040                 nvme_admin_opcode_name(nvme_admin_sanitize_nvm),        \
1041                 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1042
1043 enum {
1044         NVME_QUEUE_PHYS_CONTIG  = (1 << 0),
1045         NVME_CQ_IRQ_ENABLED     = (1 << 1),
1046         NVME_SQ_PRIO_URGENT     = (0 << 1),
1047         NVME_SQ_PRIO_HIGH       = (1 << 1),
1048         NVME_SQ_PRIO_MEDIUM     = (2 << 1),
1049         NVME_SQ_PRIO_LOW        = (3 << 1),
1050         NVME_FEAT_ARBITRATION   = 0x01,
1051         NVME_FEAT_POWER_MGMT    = 0x02,
1052         NVME_FEAT_LBA_RANGE     = 0x03,
1053         NVME_FEAT_TEMP_THRESH   = 0x04,
1054         NVME_FEAT_ERR_RECOVERY  = 0x05,
1055         NVME_FEAT_VOLATILE_WC   = 0x06,
1056         NVME_FEAT_NUM_QUEUES    = 0x07,
1057         NVME_FEAT_IRQ_COALESCE  = 0x08,
1058         NVME_FEAT_IRQ_CONFIG    = 0x09,
1059         NVME_FEAT_WRITE_ATOMIC  = 0x0a,
1060         NVME_FEAT_ASYNC_EVENT   = 0x0b,
1061         NVME_FEAT_AUTO_PST      = 0x0c,
1062         NVME_FEAT_HOST_MEM_BUF  = 0x0d,
1063         NVME_FEAT_TIMESTAMP     = 0x0e,
1064         NVME_FEAT_KATO          = 0x0f,
1065         NVME_FEAT_HCTM          = 0x10,
1066         NVME_FEAT_NOPSC         = 0x11,
1067         NVME_FEAT_RRL           = 0x12,
1068         NVME_FEAT_PLM_CONFIG    = 0x13,
1069         NVME_FEAT_PLM_WINDOW    = 0x14,
1070         NVME_FEAT_HOST_BEHAVIOR = 0x16,
1071         NVME_FEAT_SANITIZE      = 0x17,
1072         NVME_FEAT_SW_PROGRESS   = 0x80,
1073         NVME_FEAT_HOST_ID       = 0x81,
1074         NVME_FEAT_RESV_MASK     = 0x82,
1075         NVME_FEAT_RESV_PERSIST  = 0x83,
1076         NVME_FEAT_WRITE_PROTECT = 0x84,
1077         NVME_FEAT_VENDOR_START  = 0xC0,
1078         NVME_FEAT_VENDOR_END    = 0xFF,
1079         NVME_LOG_ERROR          = 0x01,
1080         NVME_LOG_SMART          = 0x02,
1081         NVME_LOG_FW_SLOT        = 0x03,
1082         NVME_LOG_CHANGED_NS     = 0x04,
1083         NVME_LOG_CMD_EFFECTS    = 0x05,
1084         NVME_LOG_DEVICE_SELF_TEST = 0x06,
1085         NVME_LOG_TELEMETRY_HOST = 0x07,
1086         NVME_LOG_TELEMETRY_CTRL = 0x08,
1087         NVME_LOG_ENDURANCE_GROUP = 0x09,
1088         NVME_LOG_ANA            = 0x0c,
1089         NVME_LOG_DISC           = 0x70,
1090         NVME_LOG_RESERVATION    = 0x80,
1091         NVME_FWACT_REPL         = (0 << 3),
1092         NVME_FWACT_REPL_ACTV    = (1 << 3),
1093         NVME_FWACT_ACTV         = (2 << 3),
1094 };
1095
1096 /* NVMe Namespace Write Protect State */
1097 enum {
1098         NVME_NS_NO_WRITE_PROTECT = 0,
1099         NVME_NS_WRITE_PROTECT,
1100         NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1101         NVME_NS_WRITE_PROTECT_PERMANENT,
1102 };
1103
1104 #define NVME_MAX_CHANGED_NAMESPACES     1024
1105
1106 struct nvme_identify {
1107         __u8                    opcode;
1108         __u8                    flags;
1109         __u16                   command_id;
1110         __le32                  nsid;
1111         __u64                   rsvd2[2];
1112         union nvme_data_ptr     dptr;
1113         __u8                    cns;
1114         __u8                    rsvd3;
1115         __le16                  ctrlid;
1116         __u8                    rsvd11[3];
1117         __u8                    csi;
1118         __u32                   rsvd12[4];
1119 };
1120
1121 #define NVME_IDENTIFY_DATA_SIZE 4096
1122
1123 struct nvme_features {
1124         __u8                    opcode;
1125         __u8                    flags;
1126         __u16                   command_id;
1127         __le32                  nsid;
1128         __u64                   rsvd2[2];
1129         union nvme_data_ptr     dptr;
1130         __le32                  fid;
1131         __le32                  dword11;
1132         __le32                  dword12;
1133         __le32                  dword13;
1134         __le32                  dword14;
1135         __le32                  dword15;
1136 };
1137
1138 struct nvme_host_mem_buf_desc {
1139         __le64                  addr;
1140         __le32                  size;
1141         __u32                   rsvd;
1142 };
1143
1144 struct nvme_create_cq {
1145         __u8                    opcode;
1146         __u8                    flags;
1147         __u16                   command_id;
1148         __u32                   rsvd1[5];
1149         __le64                  prp1;
1150         __u64                   rsvd8;
1151         __le16                  cqid;
1152         __le16                  qsize;
1153         __le16                  cq_flags;
1154         __le16                  irq_vector;
1155         __u32                   rsvd12[4];
1156 };
1157
1158 struct nvme_create_sq {
1159         __u8                    opcode;
1160         __u8                    flags;
1161         __u16                   command_id;
1162         __u32                   rsvd1[5];
1163         __le64                  prp1;
1164         __u64                   rsvd8;
1165         __le16                  sqid;
1166         __le16                  qsize;
1167         __le16                  sq_flags;
1168         __le16                  cqid;
1169         __u32                   rsvd12[4];
1170 };
1171
1172 struct nvme_delete_queue {
1173         __u8                    opcode;
1174         __u8                    flags;
1175         __u16                   command_id;
1176         __u32                   rsvd1[9];
1177         __le16                  qid;
1178         __u16                   rsvd10;
1179         __u32                   rsvd11[5];
1180 };
1181
1182 struct nvme_abort_cmd {
1183         __u8                    opcode;
1184         __u8                    flags;
1185         __u16                   command_id;
1186         __u32                   rsvd1[9];
1187         __le16                  sqid;
1188         __u16                   cid;
1189         __u32                   rsvd11[5];
1190 };
1191
1192 struct nvme_download_firmware {
1193         __u8                    opcode;
1194         __u8                    flags;
1195         __u16                   command_id;
1196         __u32                   rsvd1[5];
1197         union nvme_data_ptr     dptr;
1198         __le32                  numd;
1199         __le32                  offset;
1200         __u32                   rsvd12[4];
1201 };
1202
1203 struct nvme_format_cmd {
1204         __u8                    opcode;
1205         __u8                    flags;
1206         __u16                   command_id;
1207         __le32                  nsid;
1208         __u64                   rsvd2[4];
1209         __le32                  cdw10;
1210         __u32                   rsvd11[5];
1211 };
1212
1213 struct nvme_get_log_page_command {
1214         __u8                    opcode;
1215         __u8                    flags;
1216         __u16                   command_id;
1217         __le32                  nsid;
1218         __u64                   rsvd2[2];
1219         union nvme_data_ptr     dptr;
1220         __u8                    lid;
1221         __u8                    lsp; /* upper 4 bits reserved */
1222         __le16                  numdl;
1223         __le16                  numdu;
1224         __u16                   rsvd11;
1225         union {
1226                 struct {
1227                         __le32 lpol;
1228                         __le32 lpou;
1229                 };
1230                 __le64 lpo;
1231         };
1232         __u8                    rsvd14[3];
1233         __u8                    csi;
1234         __u32                   rsvd15;
1235 };
1236
1237 struct nvme_directive_cmd {
1238         __u8                    opcode;
1239         __u8                    flags;
1240         __u16                   command_id;
1241         __le32                  nsid;
1242         __u64                   rsvd2[2];
1243         union nvme_data_ptr     dptr;
1244         __le32                  numd;
1245         __u8                    doper;
1246         __u8                    dtype;
1247         __le16                  dspec;
1248         __u8                    endir;
1249         __u8                    tdtype;
1250         __u16                   rsvd15;
1251
1252         __u32                   rsvd16[3];
1253 };
1254
1255 /*
1256  * Fabrics subcommands.
1257  */
1258 enum nvmf_fabrics_opcode {
1259         nvme_fabrics_command            = 0x7f,
1260 };
1261
1262 enum nvmf_capsule_command {
1263         nvme_fabrics_type_property_set  = 0x00,
1264         nvme_fabrics_type_connect       = 0x01,
1265         nvme_fabrics_type_property_get  = 0x04,
1266 };
1267
1268 #define nvme_fabrics_type_name(type)   { type, #type }
1269 #define show_fabrics_type_name(type)                                    \
1270         __print_symbolic(type,                                          \
1271                 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1272                 nvme_fabrics_type_name(nvme_fabrics_type_connect),      \
1273                 nvme_fabrics_type_name(nvme_fabrics_type_property_get))
1274
1275 /*
1276  * If not fabrics command, fctype will be ignored.
1277  */
1278 #define show_opcode_name(qid, opcode, fctype)                   \
1279         ((opcode) == nvme_fabrics_command ?                     \
1280          show_fabrics_type_name(fctype) :                       \
1281         ((qid) ?                                                \
1282          show_nvm_opcode_name(opcode) :                         \
1283          show_admin_opcode_name(opcode)))
1284
1285 struct nvmf_common_command {
1286         __u8    opcode;
1287         __u8    resv1;
1288         __u16   command_id;
1289         __u8    fctype;
1290         __u8    resv2[35];
1291         __u8    ts[24];
1292 };
1293
1294 /*
1295  * The legal cntlid range a NVMe Target will provide.
1296  * Note that cntlid of value 0 is considered illegal in the fabrics world.
1297  * Devices based on earlier specs did not have the subsystem concept;
1298  * therefore, those devices had their cntlid value set to 0 as a result.
1299  */
1300 #define NVME_CNTLID_MIN         1
1301 #define NVME_CNTLID_MAX         0xffef
1302 #define NVME_CNTLID_DYNAMIC     0xffff
1303
1304 #define MAX_DISC_LOGS   255
1305
1306 /* Discovery log page entry */
1307 struct nvmf_disc_rsp_page_entry {
1308         __u8            trtype;
1309         __u8            adrfam;
1310         __u8            subtype;
1311         __u8            treq;
1312         __le16          portid;
1313         __le16          cntlid;
1314         __le16          asqsz;
1315         __u8            resv8[22];
1316         char            trsvcid[NVMF_TRSVCID_SIZE];
1317         __u8            resv64[192];
1318         char            subnqn[NVMF_NQN_FIELD_LEN];
1319         char            traddr[NVMF_TRADDR_SIZE];
1320         union tsas {
1321                 char            common[NVMF_TSAS_SIZE];
1322                 struct rdma {
1323                         __u8    qptype;
1324                         __u8    prtype;
1325                         __u8    cms;
1326                         __u8    resv3[5];
1327                         __u16   pkey;
1328                         __u8    resv10[246];
1329                 } rdma;
1330         } tsas;
1331 };
1332
1333 /* Discovery log page header */
1334 struct nvmf_disc_rsp_page_hdr {
1335         __le64          genctr;
1336         __le64          numrec;
1337         __le16          recfmt;
1338         __u8            resv14[1006];
1339         struct nvmf_disc_rsp_page_entry entries[];
1340 };
1341
1342 enum {
1343         NVME_CONNECT_DISABLE_SQFLOW     = (1 << 2),
1344 };
1345
1346 struct nvmf_connect_command {
1347         __u8            opcode;
1348         __u8            resv1;
1349         __u16           command_id;
1350         __u8            fctype;
1351         __u8            resv2[19];
1352         union nvme_data_ptr dptr;
1353         __le16          recfmt;
1354         __le16          qid;
1355         __le16          sqsize;
1356         __u8            cattr;
1357         __u8            resv3;
1358         __le32          kato;
1359         __u8            resv4[12];
1360 };
1361
1362 struct nvmf_connect_data {
1363         uuid_t          hostid;
1364         __le16          cntlid;
1365         char            resv4[238];
1366         char            subsysnqn[NVMF_NQN_FIELD_LEN];
1367         char            hostnqn[NVMF_NQN_FIELD_LEN];
1368         char            resv5[256];
1369 };
1370
1371 struct nvmf_property_set_command {
1372         __u8            opcode;
1373         __u8            resv1;
1374         __u16           command_id;
1375         __u8            fctype;
1376         __u8            resv2[35];
1377         __u8            attrib;
1378         __u8            resv3[3];
1379         __le32          offset;
1380         __le64          value;
1381         __u8            resv4[8];
1382 };
1383
1384 struct nvmf_property_get_command {
1385         __u8            opcode;
1386         __u8            resv1;
1387         __u16           command_id;
1388         __u8            fctype;
1389         __u8            resv2[35];
1390         __u8            attrib;
1391         __u8            resv3[3];
1392         __le32          offset;
1393         __u8            resv4[16];
1394 };
1395
1396 struct nvme_dbbuf {
1397         __u8                    opcode;
1398         __u8                    flags;
1399         __u16                   command_id;
1400         __u32                   rsvd1[5];
1401         __le64                  prp1;
1402         __le64                  prp2;
1403         __u32                   rsvd12[6];
1404 };
1405
1406 struct streams_directive_params {
1407         __le16  msl;
1408         __le16  nssa;
1409         __le16  nsso;
1410         __u8    rsvd[10];
1411         __le32  sws;
1412         __le16  sgs;
1413         __le16  nsa;
1414         __le16  nso;
1415         __u8    rsvd2[6];
1416 };
1417
1418 struct nvme_command {
1419         union {
1420                 struct nvme_common_command common;
1421                 struct nvme_rw_command rw;
1422                 struct nvme_identify identify;
1423                 struct nvme_features features;
1424                 struct nvme_create_cq create_cq;
1425                 struct nvme_create_sq create_sq;
1426                 struct nvme_delete_queue delete_queue;
1427                 struct nvme_download_firmware dlfw;
1428                 struct nvme_format_cmd format;
1429                 struct nvme_dsm_cmd dsm;
1430                 struct nvme_write_zeroes_cmd write_zeroes;
1431                 struct nvme_zone_mgmt_send_cmd zms;
1432                 struct nvme_zone_mgmt_recv_cmd zmr;
1433                 struct nvme_abort_cmd abort;
1434                 struct nvme_get_log_page_command get_log_page;
1435                 struct nvmf_common_command fabrics;
1436                 struct nvmf_connect_command connect;
1437                 struct nvmf_property_set_command prop_set;
1438                 struct nvmf_property_get_command prop_get;
1439                 struct nvme_dbbuf dbbuf;
1440                 struct nvme_directive_cmd directive;
1441         };
1442 };
1443
1444 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1445 {
1446         return cmd->common.opcode == nvme_fabrics_command;
1447 }
1448
1449 struct nvme_error_slot {
1450         __le64          error_count;
1451         __le16          sqid;
1452         __le16          cmdid;
1453         __le16          status_field;
1454         __le16          param_error_location;
1455         __le64          lba;
1456         __le32          nsid;
1457         __u8            vs;
1458         __u8            resv[3];
1459         __le64          cs;
1460         __u8            resv2[24];
1461 };
1462
1463 static inline bool nvme_is_write(struct nvme_command *cmd)
1464 {
1465         /*
1466          * What a mess...
1467          *
1468          * Why can't we simply have a Fabrics In and Fabrics out command?
1469          */
1470         if (unlikely(nvme_is_fabrics(cmd)))
1471                 return cmd->fabrics.fctype & 1;
1472         return cmd->common.opcode & 1;
1473 }
1474
1475 enum {
1476         /*
1477          * Generic Command Status:
1478          */
1479         NVME_SC_SUCCESS                 = 0x0,
1480         NVME_SC_INVALID_OPCODE          = 0x1,
1481         NVME_SC_INVALID_FIELD           = 0x2,
1482         NVME_SC_CMDID_CONFLICT          = 0x3,
1483         NVME_SC_DATA_XFER_ERROR         = 0x4,
1484         NVME_SC_POWER_LOSS              = 0x5,
1485         NVME_SC_INTERNAL                = 0x6,
1486         NVME_SC_ABORT_REQ               = 0x7,
1487         NVME_SC_ABORT_QUEUE             = 0x8,
1488         NVME_SC_FUSED_FAIL              = 0x9,
1489         NVME_SC_FUSED_MISSING           = 0xa,
1490         NVME_SC_INVALID_NS              = 0xb,
1491         NVME_SC_CMD_SEQ_ERROR           = 0xc,
1492         NVME_SC_SGL_INVALID_LAST        = 0xd,
1493         NVME_SC_SGL_INVALID_COUNT       = 0xe,
1494         NVME_SC_SGL_INVALID_DATA        = 0xf,
1495         NVME_SC_SGL_INVALID_METADATA    = 0x10,
1496         NVME_SC_SGL_INVALID_TYPE        = 0x11,
1497         NVME_SC_CMB_INVALID_USE         = 0x12,
1498         NVME_SC_PRP_INVALID_OFFSET      = 0x13,
1499         NVME_SC_ATOMIC_WU_EXCEEDED      = 0x14,
1500         NVME_SC_OP_DENIED               = 0x15,
1501         NVME_SC_SGL_INVALID_OFFSET      = 0x16,
1502         NVME_SC_RESERVED                = 0x17,
1503         NVME_SC_HOST_ID_INCONSIST       = 0x18,
1504         NVME_SC_KA_TIMEOUT_EXPIRED      = 0x19,
1505         NVME_SC_KA_TIMEOUT_INVALID      = 0x1A,
1506         NVME_SC_ABORTED_PREEMPT_ABORT   = 0x1B,
1507         NVME_SC_SANITIZE_FAILED         = 0x1C,
1508         NVME_SC_SANITIZE_IN_PROGRESS    = 0x1D,
1509         NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1510         NVME_SC_CMD_NOT_SUP_CMB_QUEUE   = 0x1F,
1511         NVME_SC_NS_WRITE_PROTECTED      = 0x20,
1512         NVME_SC_CMD_INTERRUPTED         = 0x21,
1513         NVME_SC_TRANSIENT_TR_ERR        = 0x22,
1514         NVME_SC_INVALID_IO_CMD_SET      = 0x2C,
1515
1516         NVME_SC_LBA_RANGE               = 0x80,
1517         NVME_SC_CAP_EXCEEDED            = 0x81,
1518         NVME_SC_NS_NOT_READY            = 0x82,
1519         NVME_SC_RESERVATION_CONFLICT    = 0x83,
1520         NVME_SC_FORMAT_IN_PROGRESS      = 0x84,
1521
1522         /*
1523          * Command Specific Status:
1524          */
1525         NVME_SC_CQ_INVALID              = 0x100,
1526         NVME_SC_QID_INVALID             = 0x101,
1527         NVME_SC_QUEUE_SIZE              = 0x102,
1528         NVME_SC_ABORT_LIMIT             = 0x103,
1529         NVME_SC_ABORT_MISSING           = 0x104,
1530         NVME_SC_ASYNC_LIMIT             = 0x105,
1531         NVME_SC_FIRMWARE_SLOT           = 0x106,
1532         NVME_SC_FIRMWARE_IMAGE          = 0x107,
1533         NVME_SC_INVALID_VECTOR          = 0x108,
1534         NVME_SC_INVALID_LOG_PAGE        = 0x109,
1535         NVME_SC_INVALID_FORMAT          = 0x10a,
1536         NVME_SC_FW_NEEDS_CONV_RESET     = 0x10b,
1537         NVME_SC_INVALID_QUEUE           = 0x10c,
1538         NVME_SC_FEATURE_NOT_SAVEABLE    = 0x10d,
1539         NVME_SC_FEATURE_NOT_CHANGEABLE  = 0x10e,
1540         NVME_SC_FEATURE_NOT_PER_NS      = 0x10f,
1541         NVME_SC_FW_NEEDS_SUBSYS_RESET   = 0x110,
1542         NVME_SC_FW_NEEDS_RESET          = 0x111,
1543         NVME_SC_FW_NEEDS_MAX_TIME       = 0x112,
1544         NVME_SC_FW_ACTIVATE_PROHIBITED  = 0x113,
1545         NVME_SC_OVERLAPPING_RANGE       = 0x114,
1546         NVME_SC_NS_INSUFFICIENT_CAP     = 0x115,
1547         NVME_SC_NS_ID_UNAVAILABLE       = 0x116,
1548         NVME_SC_NS_ALREADY_ATTACHED     = 0x118,
1549         NVME_SC_NS_IS_PRIVATE           = 0x119,
1550         NVME_SC_NS_NOT_ATTACHED         = 0x11a,
1551         NVME_SC_THIN_PROV_NOT_SUPP      = 0x11b,
1552         NVME_SC_CTRL_LIST_INVALID       = 0x11c,
1553         NVME_SC_SELT_TEST_IN_PROGRESS   = 0x11d,
1554         NVME_SC_BP_WRITE_PROHIBITED     = 0x11e,
1555         NVME_SC_CTRL_ID_INVALID         = 0x11f,
1556         NVME_SC_SEC_CTRL_STATE_INVALID  = 0x120,
1557         NVME_SC_CTRL_RES_NUM_INVALID    = 0x121,
1558         NVME_SC_RES_ID_INVALID          = 0x122,
1559         NVME_SC_PMR_SAN_PROHIBITED      = 0x123,
1560         NVME_SC_ANA_GROUP_ID_INVALID    = 0x124,
1561         NVME_SC_ANA_ATTACH_FAILED       = 0x125,
1562
1563         /*
1564          * I/O Command Set Specific - NVM commands:
1565          */
1566         NVME_SC_BAD_ATTRIBUTES          = 0x180,
1567         NVME_SC_INVALID_PI              = 0x181,
1568         NVME_SC_READ_ONLY               = 0x182,
1569         NVME_SC_ONCS_NOT_SUPPORTED      = 0x183,
1570
1571         /*
1572          * I/O Command Set Specific - Fabrics commands:
1573          */
1574         NVME_SC_CONNECT_FORMAT          = 0x180,
1575         NVME_SC_CONNECT_CTRL_BUSY       = 0x181,
1576         NVME_SC_CONNECT_INVALID_PARAM   = 0x182,
1577         NVME_SC_CONNECT_RESTART_DISC    = 0x183,
1578         NVME_SC_CONNECT_INVALID_HOST    = 0x184,
1579
1580         NVME_SC_DISCOVERY_RESTART       = 0x190,
1581         NVME_SC_AUTH_REQUIRED           = 0x191,
1582
1583         /*
1584          * I/O Command Set Specific - Zoned commands:
1585          */
1586         NVME_SC_ZONE_BOUNDARY_ERROR     = 0x1b8,
1587         NVME_SC_ZONE_FULL               = 0x1b9,
1588         NVME_SC_ZONE_READ_ONLY          = 0x1ba,
1589         NVME_SC_ZONE_OFFLINE            = 0x1bb,
1590         NVME_SC_ZONE_INVALID_WRITE      = 0x1bc,
1591         NVME_SC_ZONE_TOO_MANY_ACTIVE    = 0x1bd,
1592         NVME_SC_ZONE_TOO_MANY_OPEN      = 0x1be,
1593         NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1594
1595         /*
1596          * Media and Data Integrity Errors:
1597          */
1598         NVME_SC_WRITE_FAULT             = 0x280,
1599         NVME_SC_READ_ERROR              = 0x281,
1600         NVME_SC_GUARD_CHECK             = 0x282,
1601         NVME_SC_APPTAG_CHECK            = 0x283,
1602         NVME_SC_REFTAG_CHECK            = 0x284,
1603         NVME_SC_COMPARE_FAILED          = 0x285,
1604         NVME_SC_ACCESS_DENIED           = 0x286,
1605         NVME_SC_UNWRITTEN_BLOCK         = 0x287,
1606
1607         /*
1608          * Path-related Errors:
1609          */
1610         NVME_SC_ANA_PERSISTENT_LOSS     = 0x301,
1611         NVME_SC_ANA_INACCESSIBLE        = 0x302,
1612         NVME_SC_ANA_TRANSITION          = 0x303,
1613         NVME_SC_HOST_PATH_ERROR         = 0x370,
1614         NVME_SC_HOST_ABORTED_CMD        = 0x371,
1615
1616         NVME_SC_CRD                     = 0x1800,
1617         NVME_SC_DNR                     = 0x4000,
1618 };
1619
1620 struct nvme_completion {
1621         /*
1622          * Used by Admin and Fabrics commands to return data:
1623          */
1624         union nvme_result {
1625                 __le16  u16;
1626                 __le32  u32;
1627                 __le64  u64;
1628         } result;
1629         __le16  sq_head;        /* how much of this queue may be reclaimed */
1630         __le16  sq_id;          /* submission queue that generated this entry */
1631         __u16   command_id;     /* of the command which completed */
1632         __le16  status;         /* did the command fail, and if so, why? */
1633 };
1634
1635 #define NVME_VS(major, minor, tertiary) \
1636         (((major) << 16) | ((minor) << 8) | (tertiary))
1637
1638 #define NVME_MAJOR(ver)         ((ver) >> 16)
1639 #define NVME_MINOR(ver)         (((ver) >> 8) & 0xff)
1640 #define NVME_TERTIARY(ver)      ((ver) & 0xff)
1641
1642 #endif /* _LINUX_NVME_H */