drivers/spi/spi-pxa2xx.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   4  * Copyright (C) 2013, Intel Corporation
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/bitops.h>
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/device.h>
  12 #include <linux/err.h>
  13 #include <linux/errno.h>
  14 #include <linux/gpio/consumer.h>
  15 #include <linux/gpio.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/ioport.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/mod_devicetable.h>
  22 #include <linux/of.h>
  23 #include <linux/pci.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/property.h>
  27 #include <linux/slab.h>
  28 #include <linux/spi/pxa2xx_spi.h>
  29 #include <linux/spi/spi.h>
  30
  31 #include "spi-pxa2xx.h"
  32
  33 MODULE_AUTHOR("Stephen Street");
  34 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
  35 MODULE_LICENSE("GPL");
  36 MODULE_ALIAS("platform:pxa2xx-spi");
  37
  38 #define TIMOUT_DFLT             1000
  39
  40 /*
  41  * for testing SSCR1 changes that require SSP restart, basically
  42  * everything except the service and interrupt enables, the pxa270 developer
  43  * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
  44  * list, but the PXA255 dev man says all bits without really meaning the
  45  * service and interrupt enables
  46  */
  47 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  48                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  49                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  50                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  51                                 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
  52                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  53
  54 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF   \
  55                                 | QUARK_X1000_SSCR1_EFWR        \
  56                                 | QUARK_X1000_SSCR1_RFT         \
  57                                 | QUARK_X1000_SSCR1_TFT         \
  58                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  59
  60 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  61                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  62                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  63                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  64                                 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
  65                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  66
  67 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE   BIT(24)
  68 #define LPSS_CS_CONTROL_SW_MODE                 BIT(0)
  69 #define LPSS_CS_CONTROL_CS_HIGH                 BIT(1)
  70 #define LPSS_CAPS_CS_EN_SHIFT                   9
  71 #define LPSS_CAPS_CS_EN_MASK                    (0xf << LPSS_CAPS_CS_EN_SHIFT)
  72
  73 #define LPSS_PRIV_CLOCK_GATE 0x38
  74 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
  75 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
  76
  77 struct lpss_config {
  78         /* LPSS offset from drv_data->ioaddr */
  79         unsigned offset;
  80         /* Register offsets from drv_data->lpss_base or -1 */
  81         int reg_general;
  82         int reg_ssp;
  83         int reg_cs_ctrl;
  84         int reg_capabilities;
  85         /* FIFO thresholds */
  86         u32 rx_threshold;
  87         u32 tx_threshold_lo;
  88         u32 tx_threshold_hi;
  89         /* Chip select control */
  90         unsigned cs_sel_shift;
  91         unsigned cs_sel_mask;
  92         unsigned cs_num;
  93         /* Quirks */
  94         unsigned cs_clk_stays_gated : 1;
  95 };
  96
  97 /* Keep these sorted with enum pxa_ssp_type */
  98 static const struct lpss_config lpss_platforms[] = {
  99         {       /* LPSS_LPT_SSP */
 100                 .offset = 0x800,
 101                 .reg_general = 0x08,
 102                 .reg_ssp = 0x0c,
 103                 .reg_cs_ctrl = 0x18,
 104                 .reg_capabilities = -1,
 105                 .rx_threshold = 64,
 106                 .tx_threshold_lo = 160,
 107                 .tx_threshold_hi = 224,
 108         },
 109         {       /* LPSS_BYT_SSP */
 110                 .offset = 0x400,
 111                 .reg_general = 0x08,
 112                 .reg_ssp = 0x0c,
 113                 .reg_cs_ctrl = 0x18,
 114                 .reg_capabilities = -1,
 115                 .rx_threshold = 64,
 116                 .tx_threshold_lo = 160,
 117                 .tx_threshold_hi = 224,
 118         },
 119         {       /* LPSS_BSW_SSP */
 120                 .offset = 0x400,
 121                 .reg_general = 0x08,
 122                 .reg_ssp = 0x0c,
 123                 .reg_cs_ctrl = 0x18,
 124                 .reg_capabilities = -1,
 125                 .rx_threshold = 64,
 126                 .tx_threshold_lo = 160,
 127                 .tx_threshold_hi = 224,
 128                 .cs_sel_shift = 2,
 129                 .cs_sel_mask = 1 << 2,
 130                 .cs_num = 2,
 131         },
 132         {       /* LPSS_SPT_SSP */
 133                 .offset = 0x200,
 134                 .reg_general = -1,
 135                 .reg_ssp = 0x20,
 136                 .reg_cs_ctrl = 0x24,
 137                 .reg_capabilities = -1,
 138                 .rx_threshold = 1,
 139                 .tx_threshold_lo = 32,
 140                 .tx_threshold_hi = 56,
 141         },
 142         {       /* LPSS_BXT_SSP */
 143                 .offset = 0x200,
 144                 .reg_general = -1,
 145                 .reg_ssp = 0x20,
 146                 .reg_cs_ctrl = 0x24,
 147                 .reg_capabilities = 0xfc,
 148                 .rx_threshold = 1,
 149                 .tx_threshold_lo = 16,
 150                 .tx_threshold_hi = 48,
 151                 .cs_sel_shift = 8,
 152                 .cs_sel_mask = 3 << 8,
 153                 .cs_clk_stays_gated = true,
 154         },
 155         {       /* LPSS_CNL_SSP */
 156                 .offset = 0x200,
 157                 .reg_general = -1,
 158                 .reg_ssp = 0x20,
 159                 .reg_cs_ctrl = 0x24,
 160                 .reg_capabilities = 0xfc,
 161                 .rx_threshold = 1,
 162                 .tx_threshold_lo = 32,
 163                 .tx_threshold_hi = 56,
 164                 .cs_sel_shift = 8,
 165                 .cs_sel_mask = 3 << 8,
 166                 .cs_clk_stays_gated = true,
 167         },
 168 };
 169
 170 static inline const struct lpss_config
 171 *lpss_get_config(const struct driver_data *drv_data)
 172 {
 173         return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
 174 }
 175
 176 static bool is_lpss_ssp(const struct driver_data *drv_data)
 177 {
 178         switch (drv_data->ssp_type) {
 179         case LPSS_LPT_SSP:
 180         case LPSS_BYT_SSP:
 181         case LPSS_BSW_SSP:
 182         case LPSS_SPT_SSP:
 183         case LPSS_BXT_SSP:
 184         case LPSS_CNL_SSP:
 185                 return true;
 186         default:
 187                 return false;
 188         }
 189 }
 190
 191 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
 192 {
 193         return drv_data->ssp_type == QUARK_X1000_SSP;
 194 }
 195
 196 static bool is_mmp2_ssp(const struct driver_data *drv_data)
 197 {
 198         return drv_data->ssp_type == MMP2_SSP;
 199 }
 200
 201 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
 202 {
 203         switch (drv_data->ssp_type) {
 204         case QUARK_X1000_SSP:
 205                 return QUARK_X1000_SSCR1_CHANGE_MASK;
 206         case CE4100_SSP:
 207                 return CE4100_SSCR1_CHANGE_MASK;
 208         default:
 209                 return SSCR1_CHANGE_MASK;
 210         }
 211 }
 212
 213 static u32
 214 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
 215 {
 216         switch (drv_data->ssp_type) {
 217         case QUARK_X1000_SSP:
 218                 return RX_THRESH_QUARK_X1000_DFLT;
 219         case CE4100_SSP:
 220                 return RX_THRESH_CE4100_DFLT;
 221         default:
 222                 return RX_THRESH_DFLT;
 223         }
 224 }
 225
 226 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
 227 {
 228         u32 mask;
 229
 230         switch (drv_data->ssp_type) {
 231         case QUARK_X1000_SSP:
 232                 mask = QUARK_X1000_SSSR_TFL_MASK;
 233                 break;
 234         case CE4100_SSP:
 235                 mask = CE4100_SSSR_TFL_MASK;
 236                 break;
 237         default:
 238                 mask = SSSR_TFL_MASK;
 239                 break;
 240         }
 241
 242         return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
 243 }
 244
 245 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
 246                                      u32 *sccr1_reg)
 247 {
 248         u32 mask;
 249
 250         switch (drv_data->ssp_type) {
 251         case QUARK_X1000_SSP:
 252                 mask = QUARK_X1000_SSCR1_RFT;
 253                 break;
 254         case CE4100_SSP:
 255                 mask = CE4100_SSCR1_RFT;
 256                 break;
 257         default:
 258                 mask = SSCR1_RFT;
 259                 break;
 260         }
 261         *sccr1_reg &= ~mask;
 262 }
 263
 264 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
 265                                    u32 *sccr1_reg, u32 threshold)
 266 {
 267         switch (drv_data->ssp_type) {
 268         case QUARK_X1000_SSP:
 269                 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
 270                 break;
 271         case CE4100_SSP:
 272                 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
 273                 break;
 274         default:
 275                 *sccr1_reg |= SSCR1_RxTresh(threshold);
 276                 break;
 277         }
 278 }
 279
 280 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
 281                                   u32 clk_div, u8 bits)
 282 {
 283         switch (drv_data->ssp_type) {
 284         case QUARK_X1000_SSP:
 285                 return clk_div
 286                         | QUARK_X1000_SSCR0_Motorola
 287                         | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
 288                         | SSCR0_SSE;
 289         default:
 290                 return clk_div
 291                         | SSCR0_Motorola
 292                         | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
 293                         | SSCR0_SSE
 294                         | (bits > 16 ? SSCR0_EDSS : 0);
 295         }
 296 }
 297
 298 /*
 299  * Read and write LPSS SSP private registers. Caller must first check that
 300  * is_lpss_ssp() returns true before these can be called.
 301  */
 302 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
 303 {
 304         WARN_ON(!drv_data->lpss_base);
 305         return readl(drv_data->lpss_base + offset);
 306 }
 307
 308 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
 309                                   unsigned offset, u32 value)
 310 {
 311         WARN_ON(!drv_data->lpss_base);
 312         writel(value, drv_data->lpss_base + offset);
 313 }
 314
 315 /*
 316  * lpss_ssp_setup - perform LPSS SSP specific setup
 317  * @drv_data: pointer to the driver private data
 318  *
 319  * Perform LPSS SSP specific setup. This function must be called first if
 320  * one is going to use LPSS SSP private registers.
 321  */
 322 static void lpss_ssp_setup(struct driver_data *drv_data)
 323 {
 324         const struct lpss_config *config;
 325         u32 value;
 326
 327         config = lpss_get_config(drv_data);
 328         drv_data->lpss_base = drv_data->ioaddr + config->offset;
 329
 330         /* Enable software chip select control */
 331         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 332         value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
 333         value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
 334         __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 335
 336         /* Enable multiblock DMA transfers */
 337         if (drv_data->controller_info->enable_dma) {
 338                 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
 339
 340                 if (config->reg_general >= 0) {
 341                         value = __lpss_ssp_read_priv(drv_data,
 342                                                      config->reg_general);
 343                         value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
 344                         __lpss_ssp_write_priv(drv_data,
 345                                               config->reg_general, value);
 346                 }
 347         }
 348 }
 349
 350 static void lpss_ssp_select_cs(struct spi_device *spi,
 351                                const struct lpss_config *config)
 352 {
 353         struct driver_data *drv_data =
 354                 spi_controller_get_devdata(spi->controller);
 355         u32 value, cs;
 356
 357         if (!config->cs_sel_mask)
 358                 return;
 359
 360         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 361
 362         cs = spi->chip_select;
 363         cs <<= config->cs_sel_shift;
 364         if (cs != (value & config->cs_sel_mask)) {
 365                 /*
 366                  * When switching another chip select output active the
 367                  * output must be selected first and wait 2 ssp_clk cycles
 368                  * before changing state to active. Otherwise a short
 369                  * glitch will occur on the previous chip select since
 370                  * output select is latched but state control is not.
 371                  */
 372                 value &= ~config->cs_sel_mask;
 373                 value |= cs;
 374                 __lpss_ssp_write_priv(drv_data,
 375                                       config->reg_cs_ctrl, value);
 376                 ndelay(1000000000 /
 377                        (drv_data->controller->max_speed_hz / 2));
 378         }
 379 }
 380
 381 static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
 382 {
 383         struct driver_data *drv_data =
 384                 spi_controller_get_devdata(spi->controller);
 385         const struct lpss_config *config;
 386         u32 value;
 387
 388         config = lpss_get_config(drv_data);
 389
 390         if (enable)
 391                 lpss_ssp_select_cs(spi, config);
 392
 393         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 394         if (enable)
 395                 value &= ~LPSS_CS_CONTROL_CS_HIGH;
 396         else
 397                 value |= LPSS_CS_CONTROL_CS_HIGH;
 398         __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 399         if (config->cs_clk_stays_gated) {
 400                 u32 clkgate;
 401
 402                 /*
 403                  * Changing CS alone when dynamic clock gating is on won't
 404                  * actually flip CS at that time. This ruins SPI transfers
 405                  * that specify delays, or have no data. Toggle the clock mode
 406                  * to force on briefly to poke the CS pin to move.
 407                  */
 408                 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
 409                 value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
 410                         LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
 411
 412                 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
 413                 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
 414         }
 415 }
 416
 417 static void cs_assert(struct spi_device *spi)
 418 {
 419         struct chip_data *chip = spi_get_ctldata(spi);
 420         struct driver_data *drv_data =
 421                 spi_controller_get_devdata(spi->controller);
 422
 423         if (drv_data->ssp_type == CE4100_SSP) {
 424                 pxa2xx_spi_write(drv_data, SSSR, chip->frm);
 425                 return;
 426         }
 427
 428         if (chip->cs_control) {
 429                 chip->cs_control(PXA2XX_CS_ASSERT);
 430                 return;
 431         }
 432
 433         if (chip->gpiod_cs) {
 434                 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
 435                 return;
 436         }
 437
 438         if (is_lpss_ssp(drv_data))
 439                 lpss_ssp_cs_control(spi, true);
 440 }
 441
 442 static void cs_deassert(struct spi_device *spi)
 443 {
 444         struct chip_data *chip = spi_get_ctldata(spi);
 445         struct driver_data *drv_data =
 446                 spi_controller_get_devdata(spi->controller);
 447         unsigned long timeout;
 448
 449         if (drv_data->ssp_type == CE4100_SSP)
 450                 return;
 451
 452         /* Wait until SSP becomes idle before deasserting the CS */
 453         timeout = jiffies + msecs_to_jiffies(10);
 454         while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
 455                !time_after(jiffies, timeout))
 456                 cpu_relax();
 457
 458         if (chip->cs_control) {
 459                 chip->cs_control(PXA2XX_CS_DEASSERT);
 460                 return;
 461         }
 462
 463         if (chip->gpiod_cs) {
 464                 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
 465                 return;
 466         }
 467
 468         if (is_lpss_ssp(drv_data))
 469                 lpss_ssp_cs_control(spi, false);
 470 }
 471
 472 static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
 473 {
 474         if (level)
 475                 cs_deassert(spi);
 476         else
 477                 cs_assert(spi);
 478 }
 479
 480 int pxa2xx_spi_flush(struct driver_data *drv_data)
 481 {
 482         unsigned long limit = loops_per_jiffy << 1;
 483
 484         do {
 485                 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 486                         pxa2xx_spi_read(drv_data, SSDR);
 487         } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
 488         write_SSSR_CS(drv_data, SSSR_ROR);
 489
 490         return limit;
 491 }
 492
 493 static void pxa2xx_spi_off(struct driver_data *drv_data)
 494 {
 495         /* On MMP, disabling SSE seems to corrupt the Rx FIFO */
 496         if (is_mmp2_ssp(drv_data))
 497                 return;
 498
 499         pxa2xx_spi_write(drv_data, SSCR0,
 500                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
 501 }
 502
 503 static int null_writer(struct driver_data *drv_data)
 504 {
 505         u8 n_bytes = drv_data->n_bytes;
 506
 507         if (pxa2xx_spi_txfifo_full(drv_data)
 508                 || (drv_data->tx == drv_data->tx_end))
 509                 return 0;
 510
 511         pxa2xx_spi_write(drv_data, SSDR, 0);
 512         drv_data->tx += n_bytes;
 513
 514         return 1;
 515 }
 516
 517 static int null_reader(struct driver_data *drv_data)
 518 {
 519         u8 n_bytes = drv_data->n_bytes;
 520
 521         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 522                && (drv_data->rx < drv_data->rx_end)) {
 523                 pxa2xx_spi_read(drv_data, SSDR);
 524                 drv_data->rx += n_bytes;
 525         }
 526
 527         return drv_data->rx == drv_data->rx_end;
 528 }
 529
 530 static int u8_writer(struct driver_data *drv_data)
 531 {
 532         if (pxa2xx_spi_txfifo_full(drv_data)
 533                 || (drv_data->tx == drv_data->tx_end))
 534                 return 0;
 535
 536         pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
 537         ++drv_data->tx;
 538
 539         return 1;
 540 }
 541
 542 static int u8_reader(struct driver_data *drv_data)
 543 {
 544         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 545                && (drv_data->rx < drv_data->rx_end)) {
 546                 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 547                 ++drv_data->rx;
 548         }
 549
 550         return drv_data->rx == drv_data->rx_end;
 551 }
 552
 553 static int u16_writer(struct driver_data *drv_data)
 554 {
 555         if (pxa2xx_spi_txfifo_full(drv_data)
 556                 || (drv_data->tx == drv_data->tx_end))
 557                 return 0;
 558
 559         pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
 560         drv_data->tx += 2;
 561
 562         return 1;
 563 }
 564
 565 static int u16_reader(struct driver_data *drv_data)
 566 {
 567         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 568                && (drv_data->rx < drv_data->rx_end)) {
 569                 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 570                 drv_data->rx += 2;
 571         }
 572
 573         return drv_data->rx == drv_data->rx_end;
 574 }
 575
 576 static int u32_writer(struct driver_data *drv_data)
 577 {
 578         if (pxa2xx_spi_txfifo_full(drv_data)
 579                 || (drv_data->tx == drv_data->tx_end))
 580                 return 0;
 581
 582         pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
 583         drv_data->tx += 4;
 584
 585         return 1;
 586 }
 587
 588 static int u32_reader(struct driver_data *drv_data)
 589 {
 590         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 591                && (drv_data->rx < drv_data->rx_end)) {
 592                 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 593                 drv_data->rx += 4;
 594         }
 595
 596         return drv_data->rx == drv_data->rx_end;
 597 }
 598
 599 static void reset_sccr1(struct driver_data *drv_data)
 600 {
 601         struct chip_data *chip =
 602                 spi_get_ctldata(drv_data->controller->cur_msg->spi);
 603         u32 sccr1_reg;
 604
 605         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
 606         switch (drv_data->ssp_type) {
 607         case QUARK_X1000_SSP:
 608                 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
 609                 break;
 610         case CE4100_SSP:
 611                 sccr1_reg &= ~CE4100_SSCR1_RFT;
 612                 break;
 613         default:
 614                 sccr1_reg &= ~SSCR1_RFT;
 615                 break;
 616         }
 617         sccr1_reg |= chip->threshold;
 618         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 619 }
 620
 621 static void int_error_stop(struct driver_data *drv_data, const char *msg)
 622 {
 623         /* Stop and reset SSP */
 624         write_SSSR_CS(drv_data, drv_data->clear_sr);
 625         reset_sccr1(drv_data);
 626         if (!pxa25x_ssp_comp(drv_data))
 627                 pxa2xx_spi_write(drv_data, SSTO, 0);
 628         pxa2xx_spi_flush(drv_data);
 629         pxa2xx_spi_off(drv_data);
 630
 631         dev_err(&drv_data->pdev->dev, "%s\n", msg);
 632
 633         drv_data->controller->cur_msg->status = -EIO;
 634         spi_finalize_current_transfer(drv_data->controller);
 635 }
 636
 637 static void int_transfer_complete(struct driver_data *drv_data)
 638 {
 639         /* Clear and disable interrupts */
 640         write_SSSR_CS(drv_data, drv_data->clear_sr);
 641         reset_sccr1(drv_data);
 642         if (!pxa25x_ssp_comp(drv_data))
 643                 pxa2xx_spi_write(drv_data, SSTO, 0);
 644
 645         spi_finalize_current_transfer(drv_data->controller);
 646 }
 647
 648 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
 649 {
 650         u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
 651                        drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
 652
 653         u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
 654
 655         if (irq_status & SSSR_ROR) {
 656                 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
 657                 return IRQ_HANDLED;
 658         }
 659
 660         if (irq_status & SSSR_TUR) {
 661                 int_error_stop(drv_data, "interrupt_transfer: fifo underrun");
 662                 return IRQ_HANDLED;
 663         }
 664
 665         if (irq_status & SSSR_TINT) {
 666                 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
 667                 if (drv_data->read(drv_data)) {
 668                         int_transfer_complete(drv_data);
 669                         return IRQ_HANDLED;
 670                 }
 671         }
 672
 673         /* Drain rx fifo, Fill tx fifo and prevent overruns */
 674         do {
 675                 if (drv_data->read(drv_data)) {
 676                         int_transfer_complete(drv_data);
 677                         return IRQ_HANDLED;
 678                 }
 679         } while (drv_data->write(drv_data));
 680
 681         if (drv_data->read(drv_data)) {
 682                 int_transfer_complete(drv_data);
 683                 return IRQ_HANDLED;
 684         }
 685
 686         if (drv_data->tx == drv_data->tx_end) {
 687                 u32 bytes_left;
 688                 u32 sccr1_reg;
 689
 690                 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
 691                 sccr1_reg &= ~SSCR1_TIE;
 692
 693                 /*
 694                  * PXA25x_SSP has no timeout, set up rx threshould for the
 695                  * remaining RX bytes.
 696                  */
 697                 if (pxa25x_ssp_comp(drv_data)) {
 698                         u32 rx_thre;
 699
 700                         pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
 701
 702                         bytes_left = drv_data->rx_end - drv_data->rx;
 703                         switch (drv_data->n_bytes) {
 704                         case 4:
 705                                 bytes_left >>= 2;
 706                                 break;
 707                         case 2:
 708                                 bytes_left >>= 1;
 709                                 break;
 710                         }
 711
 712                         rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
 713                         if (rx_thre > bytes_left)
 714                                 rx_thre = bytes_left;
 715
 716                         pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
 717                 }
 718                 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 719         }
 720
 721         /* We did something */
 722         return IRQ_HANDLED;
 723 }
 724
 725 static void handle_bad_msg(struct driver_data *drv_data)
 726 {
 727         pxa2xx_spi_off(drv_data);
 728         pxa2xx_spi_write(drv_data, SSCR1,
 729                          pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
 730         if (!pxa25x_ssp_comp(drv_data))
 731                 pxa2xx_spi_write(drv_data, SSTO, 0);
 732         write_SSSR_CS(drv_data, drv_data->clear_sr);
 733
 734         dev_err(&drv_data->pdev->dev,
 735                 "bad message state in interrupt handler\n");
 736 }
 737
 738 static irqreturn_t ssp_int(int irq, void *dev_id)
 739 {
 740         struct driver_data *drv_data = dev_id;
 741         u32 sccr1_reg;
 742         u32 mask = drv_data->mask_sr;
 743         u32 status;
 744
 745         /*
 746          * The IRQ might be shared with other peripherals so we must first
 747          * check that are we RPM suspended or not. If we are we assume that
 748          * the IRQ was not for us (we shouldn't be RPM suspended when the
 749          * interrupt is enabled).
 750          */
 751         if (pm_runtime_suspended(&drv_data->pdev->dev))
 752                 return IRQ_NONE;
 753
 754         /*
 755          * If the device is not yet in RPM suspended state and we get an
 756          * interrupt that is meant for another device, check if status bits
 757          * are all set to one. That means that the device is already
 758          * powered off.
 759          */
 760         status = pxa2xx_spi_read(drv_data, SSSR);
 761         if (status == ~0)
 762                 return IRQ_NONE;
 763
 764         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
 765
 766         /* Ignore possible writes if we don't need to write */
 767         if (!(sccr1_reg & SSCR1_TIE))
 768                 mask &= ~SSSR_TFS;
 769
 770         /* Ignore RX timeout interrupt if it is disabled */
 771         if (!(sccr1_reg & SSCR1_TINTE))
 772                 mask &= ~SSSR_TINT;
 773
 774         if (!(status & mask))
 775                 return IRQ_NONE;
 776
 777         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
 778         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 779
 780         if (!drv_data->controller->cur_msg) {
 781                 handle_bad_msg(drv_data);
 782                 /* Never fail */
 783                 return IRQ_HANDLED;
 784         }
 785
 786         return drv_data->transfer_handler(drv_data);
 787 }
 788
 789 /*
 790  * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
 791  * input frequency by fractions of 2^24. It also has a divider by 5.
 792  *
 793  * There are formulas to get baud rate value for given input frequency and
 794  * divider parameters, such as DDS_CLK_RATE and SCR:
 795  *
 796  * Fsys = 200MHz
 797  *
 798  * Fssp = Fsys * DDS_CLK_RATE / 2^24                    (1)
 799  * Baud rate = Fsclk = Fssp / (2 * (SCR + 1))           (2)
 800  *
 801  * DDS_CLK_RATE either 2^n or 2^n / 5.
 802  * SCR is in range 0 .. 255
 803  *
 804  * Divisor = 5^i * 2^j * 2 * k
 805  *       i = [0, 1]      i = 1 iff j = 0 or j > 3
 806  *       j = [0, 23]     j = 0 iff i = 1
 807  *       k = [1, 256]
 808  * Special case: j = 0, i = 1: Divisor = 2 / 5
 809  *
 810  * Accordingly to the specification the recommended values for DDS_CLK_RATE
 811  * are:
 812  *      Case 1:         2^n, n = [0, 23]
 813  *      Case 2:         2^24 * 2 / 5 (0x666666)
 814  *      Case 3:         less than or equal to 2^24 / 5 / 16 (0x33333)
 815  *
 816  * In all cases the lowest possible value is better.
 817  *
 818  * The function calculates parameters for all cases and chooses the one closest
 819  * to the asked baud rate.
 820  */
 821 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
 822 {
 823         unsigned long xtal = 200000000;
 824         unsigned long fref = xtal / 2;          /* mandatory division by 2,
 825                                                    see (2) */
 826                                                 /* case 3 */
 827         unsigned long fref1 = fref / 2;         /* case 1 */
 828         unsigned long fref2 = fref * 2 / 5;     /* case 2 */
 829         unsigned long scale;
 830         unsigned long q, q1, q2;
 831         long r, r1, r2;
 832         u32 mul;
 833
 834         /* Case 1 */
 835
 836         /* Set initial value for DDS_CLK_RATE */
 837         mul = (1 << 24) >> 1;
 838
 839         /* Calculate initial quot */
 840         q1 = DIV_ROUND_UP(fref1, rate);
 841
 842         /* Scale q1 if it's too big */
 843         if (q1 > 256) {
 844                 /* Scale q1 to range [1, 512] */
 845                 scale = fls_long(q1 - 1);
 846                 if (scale > 9) {
 847                         q1 >>= scale - 9;
 848                         mul >>= scale - 9;
 849                 }
 850
 851                 /* Round the result if we have a remainder */
 852                 q1 += q1 & 1;
 853         }
 854
 855         /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
 856         scale = __ffs(q1);
 857         q1 >>= scale;
 858         mul >>= scale;
 859
 860         /* Get the remainder */
 861         r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
 862
 863         /* Case 2 */
 864
 865         q2 = DIV_ROUND_UP(fref2, rate);
 866         r2 = abs(fref2 / q2 - rate);
 867
 868         /*
 869          * Choose the best between two: less remainder we have the better. We
 870          * can't go case 2 if q2 is greater than 256 since SCR register can
 871          * hold only values 0 .. 255.
 872          */
 873         if (r2 >= r1 || q2 > 256) {
 874                 /* case 1 is better */
 875                 r = r1;
 876                 q = q1;
 877         } else {
 878                 /* case 2 is better */
 879                 r = r2;
 880                 q = q2;
 881                 mul = (1 << 24) * 2 / 5;
 882         }
 883
 884         /* Check case 3 only if the divisor is big enough */
 885         if (fref / rate >= 80) {
 886                 u64 fssp;
 887                 u32 m;
 888
 889                 /* Calculate initial quot */
 890                 q1 = DIV_ROUND_UP(fref, rate);
 891                 m = (1 << 24) / q1;
 892
 893                 /* Get the remainder */
 894                 fssp = (u64)fref * m;
 895                 do_div(fssp, 1 << 24);
 896                 r1 = abs(fssp - rate);
 897
 898                 /* Choose this one if it suits better */
 899                 if (r1 < r) {
 900                         /* case 3 is better */
 901                         q = 1;
 902                         mul = m;
 903                 }
 904         }
 905
 906         *dds = mul;
 907         return q - 1;
 908 }
 909
 910 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
 911 {
 912         unsigned long ssp_clk = drv_data->controller->max_speed_hz;
 913         const struct ssp_device *ssp = drv_data->ssp;
 914
 915         rate = min_t(int, ssp_clk, rate);
 916
 917         /*
 918          * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
 919          * that the SSP transmission rate can be greater than the device rate
 920          */
 921         if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
 922                 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
 923         else
 924                 return (DIV_ROUND_UP(ssp_clk, rate) - 1)  & 0xfff;
 925 }
 926
 927 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
 928                                            int rate)
 929 {
 930         struct chip_data *chip =
 931                 spi_get_ctldata(drv_data->controller->cur_msg->spi);
 932         unsigned int clk_div;
 933
 934         switch (drv_data->ssp_type) {
 935         case QUARK_X1000_SSP:
 936                 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
 937                 break;
 938         default:
 939                 clk_div = ssp_get_clk_div(drv_data, rate);
 940                 break;
 941         }
 942         return clk_div << 8;
 943 }
 944
 945 static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
 946                                struct spi_device *spi,
 947                                struct spi_transfer *xfer)
 948 {
 949         struct chip_data *chip = spi_get_ctldata(spi);
 950
 951         return chip->enable_dma &&
 952                xfer->len <= MAX_DMA_LEN &&
 953                xfer->len >= chip->dma_burst_size;
 954 }
 955
 956 static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
 957                                    struct spi_device *spi,
 958                                    struct spi_transfer *transfer)
 959 {
 960         struct driver_data *drv_data = spi_controller_get_devdata(controller);
 961         struct spi_message *message = controller->cur_msg;
 962         struct chip_data *chip = spi_get_ctldata(spi);
 963         u32 dma_thresh = chip->dma_threshold;
 964         u32 dma_burst = chip->dma_burst_size;
 965         u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
 966         u32 clk_div;
 967         u8 bits;
 968         u32 speed;
 969         u32 cr0;
 970         u32 cr1;
 971         int err;
 972         int dma_mapped;
 973
 974         /* Check if we can DMA this transfer */
 975         if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
 976
 977                 /* reject already-mapped transfers; PIO won't always work */
 978                 if (message->is_dma_mapped
 979                                 || transfer->rx_dma || transfer->tx_dma) {
 980                         dev_err(&spi->dev,
 981                                 "Mapped transfer length of %u is greater than %d\n",
 982                                 transfer->len, MAX_DMA_LEN);
 983                         return -EINVAL;
 984                 }
 985
 986                 /* warn ... we force this to PIO mode */
 987                 dev_warn_ratelimited(&spi->dev,
 988                                      "DMA disabled for transfer length %ld greater than %d\n",
 989                                      (long)transfer->len, MAX_DMA_LEN);
 990         }
 991
 992         /* Setup the transfer state based on the type of transfer */
 993         if (pxa2xx_spi_flush(drv_data) == 0) {
 994                 dev_err(&spi->dev, "Flush failed\n");
 995                 return -EIO;
 996         }
 997         drv_data->n_bytes = chip->n_bytes;
 998         drv_data->tx = (void *)transfer->tx_buf;
 999         drv_data->tx_end = drv_data->tx + transfer->len;
1000         drv_data->rx = transfer->rx_buf;
1001         drv_data->rx_end = drv_data->rx + transfer->len;
1002         drv_data->write = drv_data->tx ? chip->write : null_writer;
1003         drv_data->read = drv_data->rx ? chip->read : null_reader;
1004
1005         /* Change speed and bit per word on a per transfer */
1006         bits = transfer->bits_per_word;
1007         speed = transfer->speed_hz;
1008
1009         clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
1010
1011         if (bits <= 8) {
1012                 drv_data->n_bytes = 1;
1013                 drv_data->read = drv_data->read != null_reader ?
1014                                         u8_reader : null_reader;
1015                 drv_data->write = drv_data->write != null_writer ?
1016                                         u8_writer : null_writer;
1017         } else if (bits <= 16) {
1018                 drv_data->n_bytes = 2;
1019                 drv_data->read = drv_data->read != null_reader ?
1020                                         u16_reader : null_reader;
1021                 drv_data->write = drv_data->write != null_writer ?
1022                                         u16_writer : null_writer;
1023         } else if (bits <= 32) {
1024                 drv_data->n_bytes = 4;
1025                 drv_data->read = drv_data->read != null_reader ?
1026                                         u32_reader : null_reader;
1027                 drv_data->write = drv_data->write != null_writer ?
1028                                         u32_writer : null_writer;
1029         }
1030         /*
1031          * if bits/word is changed in dma mode, then must check the
1032          * thresholds and burst also
1033          */
1034         if (chip->enable_dma) {
1035                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1036                                                 spi,
1037                                                 bits, &dma_burst,
1038                                                 &dma_thresh))
1039                         dev_warn_ratelimited(&spi->dev,
1040                                              "DMA burst size reduced to match bits_per_word\n");
1041         }
1042
1043         dma_mapped = controller->can_dma &&
1044                      controller->can_dma(controller, spi, transfer) &&
1045                      controller->cur_msg_mapped;
1046         if (dma_mapped) {
1047
1048                 /* Ensure we have the correct interrupt handler */
1049                 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1050
1051                 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1052                 if (err)
1053                         return err;
1054
1055                 /* Clear status and start DMA engine */
1056                 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1057                 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1058
1059                 pxa2xx_spi_dma_start(drv_data);
1060         } else {
1061                 /* Ensure we have the correct interrupt handler */
1062                 drv_data->transfer_handler = interrupt_transfer;
1063
1064                 /* Clear status  */
1065                 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1066                 write_SSSR_CS(drv_data, drv_data->clear_sr);
1067         }
1068
1069         /* NOTE:  PXA25x_SSP _could_ use external clocking ... */
1070         cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1071         if (!pxa25x_ssp_comp(drv_data))
1072                 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1073                         controller->max_speed_hz
1074                                 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1075                         dma_mapped ? "DMA" : "PIO");
1076         else
1077                 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1078                         controller->max_speed_hz / 2
1079                                 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1080                         dma_mapped ? "DMA" : "PIO");
1081
1082         if (is_lpss_ssp(drv_data)) {
1083                 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1084                     != chip->lpss_rx_threshold)
1085                         pxa2xx_spi_write(drv_data, SSIRF,
1086                                          chip->lpss_rx_threshold);
1087                 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1088                     != chip->lpss_tx_threshold)
1089                         pxa2xx_spi_write(drv_data, SSITF,
1090                                          chip->lpss_tx_threshold);
1091         }
1092
1093         if (is_quark_x1000_ssp(drv_data) &&
1094             (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1095                 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1096
1097         /* see if we need to reload the config registers */
1098         if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1099             || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1100             != (cr1 & change_mask)) {
1101                 /* stop the SSP, and update the other bits */
1102                 if (!is_mmp2_ssp(drv_data))
1103                         pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1104                 if (!pxa25x_ssp_comp(drv_data))
1105                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1106                 /* first set CR1 without interrupt and service enables */
1107                 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1108                 /* restart the SSP */
1109                 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1110
1111         } else {
1112                 if (!pxa25x_ssp_comp(drv_data))
1113                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1114         }
1115
1116         if (is_mmp2_ssp(drv_data)) {
1117                 u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR)
1118                                         & SSSR_TFL_MASK) >> 8;
1119
1120                 if (tx_level) {
1121                         /* On MMP2, flipping SSE doesn't to empty TXFIFO. */
1122                         dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n",
1123                                                                 tx_level);
1124                         if (tx_level > transfer->len)
1125                                 tx_level = transfer->len;
1126                         drv_data->tx += tx_level;
1127                 }
1128         }
1129
1130         if (spi_controller_is_slave(controller)) {
1131                 while (drv_data->write(drv_data))
1132                         ;
1133                 if (drv_data->gpiod_ready) {
1134                         gpiod_set_value(drv_data->gpiod_ready, 1);
1135                         udelay(1);
1136                         gpiod_set_value(drv_data->gpiod_ready, 0);
1137                 }
1138         }
1139
1140         /*
1141          * Release the data by enabling service requests and interrupts,
1142          * without changing any mode bits
1143          */
1144         pxa2xx_spi_write(drv_data, SSCR1, cr1);
1145
1146         return 1;
1147 }
1148
1149 static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
1150 {
1151         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1152
1153         /* Stop and reset SSP */
1154         write_SSSR_CS(drv_data, drv_data->clear_sr);
1155         reset_sccr1(drv_data);
1156         if (!pxa25x_ssp_comp(drv_data))
1157                 pxa2xx_spi_write(drv_data, SSTO, 0);
1158         pxa2xx_spi_flush(drv_data);
1159         pxa2xx_spi_off(drv_data);
1160
1161         dev_dbg(&drv_data->pdev->dev, "transfer aborted\n");
1162
1163         drv_data->controller->cur_msg->status = -EINTR;
1164         spi_finalize_current_transfer(drv_data->controller);
1165
1166         return 0;
1167 }
1168
1169 static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1170                                  struct spi_message *msg)
1171 {
1172         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1173
1174         /* Disable the SSP */
1175         pxa2xx_spi_off(drv_data);
1176         /* Clear and disable interrupts and service requests */
1177         write_SSSR_CS(drv_data, drv_data->clear_sr);
1178         pxa2xx_spi_write(drv_data, SSCR1,
1179                          pxa2xx_spi_read(drv_data, SSCR1)
1180                          & ~(drv_data->int_cr1 | drv_data->dma_cr1));
1181         if (!pxa25x_ssp_comp(drv_data))
1182                 pxa2xx_spi_write(drv_data, SSTO, 0);
1183
1184         /*
1185          * Stop the DMA if running. Note DMA callback handler may have unset
1186          * the dma_running already, which is fine as stopping is not needed
1187          * then but we shouldn't rely this flag for anything else than
1188          * stopping. For instance to differentiate between PIO and DMA
1189          * transfers.
1190          */
1191         if (atomic_read(&drv_data->dma_running))
1192                 pxa2xx_spi_dma_stop(drv_data);
1193 }
1194
1195 static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1196 {
1197         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1198
1199         /* Disable the SSP now */
1200         pxa2xx_spi_off(drv_data);
1201
1202         return 0;
1203 }
1204
1205 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1206                     struct pxa2xx_spi_chip *chip_info)
1207 {
1208         struct driver_data *drv_data =
1209                 spi_controller_get_devdata(spi->controller);
1210         struct gpio_desc *gpiod;
1211         int err = 0;
1212
1213         if (chip == NULL)
1214                 return 0;
1215
1216         if (drv_data->cs_gpiods) {
1217                 gpiod = drv_data->cs_gpiods[spi->chip_select];
1218                 if (gpiod) {
1219                         chip->gpiod_cs = gpiod;
1220                         chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1221                         gpiod_set_value(gpiod, chip->gpio_cs_inverted);
1222                 }
1223
1224                 return 0;
1225         }
1226
1227         if (chip_info == NULL)
1228                 return 0;
1229
1230         /* NOTE: setup() can be called multiple times, possibly with
1231          * different chip_info, release previously requested GPIO
1232          */
1233         if (chip->gpiod_cs) {
1234                 gpiod_put(chip->gpiod_cs);
1235                 chip->gpiod_cs = NULL;
1236         }
1237
1238         /* If (*cs_control) is provided, ignore GPIO chip select */
1239         if (chip_info->cs_control) {
1240                 chip->cs_control = chip_info->cs_control;
1241                 return 0;
1242         }
1243
1244         if (gpio_is_valid(chip_info->gpio_cs)) {
1245                 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1246                 if (err) {
1247                         dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1248                                 chip_info->gpio_cs);
1249                         return err;
1250                 }
1251
1252                 gpiod = gpio_to_desc(chip_info->gpio_cs);
1253                 chip->gpiod_cs = gpiod;
1254                 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1255
1256                 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
1257                 if (err)
1258                         gpiod_put(chip->gpiod_cs);
1259         }
1260
1261         return err;
1262 }
1263
1264 static int setup(struct spi_device *spi)
1265 {
1266         struct pxa2xx_spi_chip *chip_info;
1267         struct chip_data *chip;
1268         const struct lpss_config *config;
1269         struct driver_data *drv_data =
1270                 spi_controller_get_devdata(spi->controller);
1271         uint tx_thres, tx_hi_thres, rx_thres;
1272         int err;
1273
1274         switch (drv_data->ssp_type) {
1275         case QUARK_X1000_SSP:
1276                 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1277                 tx_hi_thres = 0;
1278                 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1279                 break;
1280         case CE4100_SSP:
1281                 tx_thres = TX_THRESH_CE4100_DFLT;
1282                 tx_hi_thres = 0;
1283                 rx_thres = RX_THRESH_CE4100_DFLT;
1284                 break;
1285         case LPSS_LPT_SSP:
1286         case LPSS_BYT_SSP:
1287         case LPSS_BSW_SSP:
1288         case LPSS_SPT_SSP:
1289         case LPSS_BXT_SSP:
1290         case LPSS_CNL_SSP:
1291                 config = lpss_get_config(drv_data);
1292                 tx_thres = config->tx_threshold_lo;
1293                 tx_hi_thres = config->tx_threshold_hi;
1294                 rx_thres = config->rx_threshold;
1295                 break;
1296         default:
1297                 tx_hi_thres = 0;
1298                 if (spi_controller_is_slave(drv_data->controller)) {
1299                         tx_thres = 1;
1300                         rx_thres = 2;
1301                 } else {
1302                         tx_thres = TX_THRESH_DFLT;
1303                         rx_thres = RX_THRESH_DFLT;
1304                 }
1305                 break;
1306         }
1307
1308         /* Only alloc on first setup */
1309         chip = spi_get_ctldata(spi);
1310         if (!chip) {
1311                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1312                 if (!chip)
1313                         return -ENOMEM;
1314
1315                 if (drv_data->ssp_type == CE4100_SSP) {
1316                         if (spi->chip_select > 4) {
1317                                 dev_err(&spi->dev,
1318                                         "failed setup: cs number must not be > 4.\n");
1319                                 kfree(chip);
1320                                 return -EINVAL;
1321                         }
1322
1323                         chip->frm = spi->chip_select;
1324                 }
1325                 chip->enable_dma = drv_data->controller_info->enable_dma;
1326                 chip->timeout = TIMOUT_DFLT;
1327         }
1328
1329         /* protocol drivers may change the chip settings, so...
1330          * if chip_info exists, use it */
1331         chip_info = spi->controller_data;
1332
1333         /* chip_info isn't always needed */
1334         chip->cr1 = 0;
1335         if (chip_info) {
1336                 if (chip_info->timeout)
1337                         chip->timeout = chip_info->timeout;
1338                 if (chip_info->tx_threshold)
1339                         tx_thres = chip_info->tx_threshold;
1340                 if (chip_info->tx_hi_threshold)
1341                         tx_hi_thres = chip_info->tx_hi_threshold;
1342                 if (chip_info->rx_threshold)
1343                         rx_thres = chip_info->rx_threshold;
1344                 chip->dma_threshold = 0;
1345                 if (chip_info->enable_loopback)
1346                         chip->cr1 = SSCR1_LBM;
1347         }
1348         if (spi_controller_is_slave(drv_data->controller)) {
1349                 chip->cr1 |= SSCR1_SCFR;
1350                 chip->cr1 |= SSCR1_SCLKDIR;
1351                 chip->cr1 |= SSCR1_SFRMDIR;
1352                 chip->cr1 |= SSCR1_SPH;
1353         }
1354
1355         chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1356         chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1357                                 | SSITF_TxHiThresh(tx_hi_thres);
1358
1359         /* set dma burst and threshold outside of chip_info path so that if
1360          * chip_info goes away after setting chip->enable_dma, the
1361          * burst and threshold can still respond to changes in bits_per_word */
1362         if (chip->enable_dma) {
1363                 /* set up legal burst and threshold for dma */
1364                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1365                                                 spi->bits_per_word,
1366                                                 &chip->dma_burst_size,
1367                                                 &chip->dma_threshold)) {
1368                         dev_warn(&spi->dev,
1369                                  "in setup: DMA burst size reduced to match bits_per_word\n");
1370                 }
1371                 dev_dbg(&spi->dev,
1372                         "in setup: DMA burst size set to %u\n",
1373                         chip->dma_burst_size);
1374         }
1375
1376         switch (drv_data->ssp_type) {
1377         case QUARK_X1000_SSP:
1378                 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1379                                    & QUARK_X1000_SSCR1_RFT)
1380                                    | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1381                                    & QUARK_X1000_SSCR1_TFT);
1382                 break;
1383         case CE4100_SSP:
1384                 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1385                         (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1386                 break;
1387         default:
1388                 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1389                         (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1390                 break;
1391         }
1392
1393         chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1394         chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1395                         | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1396
1397         if (spi->mode & SPI_LOOP)
1398                 chip->cr1 |= SSCR1_LBM;
1399
1400         if (spi->bits_per_word <= 8) {
1401                 chip->n_bytes = 1;
1402                 chip->read = u8_reader;
1403                 chip->write = u8_writer;
1404         } else if (spi->bits_per_word <= 16) {
1405                 chip->n_bytes = 2;
1406                 chip->read = u16_reader;
1407                 chip->write = u16_writer;
1408         } else if (spi->bits_per_word <= 32) {
1409                 chip->n_bytes = 4;
1410                 chip->read = u32_reader;
1411                 chip->write = u32_writer;
1412         }
1413
1414         spi_set_ctldata(spi, chip);
1415
1416         if (drv_data->ssp_type == CE4100_SSP)
1417                 return 0;
1418
1419         err = setup_cs(spi, chip, chip_info);
1420         if (err)
1421                 kfree(chip);
1422
1423         return err;
1424 }
1425
1426 static void cleanup(struct spi_device *spi)
1427 {
1428         struct chip_data *chip = spi_get_ctldata(spi);
1429         struct driver_data *drv_data =
1430                 spi_controller_get_devdata(spi->controller);
1431
1432         if (!chip)
1433                 return;
1434
1435         if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
1436             chip->gpiod_cs)
1437                 gpiod_put(chip->gpiod_cs);
1438
1439         kfree(chip);
1440 }
1441
1442 #ifdef CONFIG_ACPI
1443 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1444         { "INT33C0", LPSS_LPT_SSP },
1445         { "INT33C1", LPSS_LPT_SSP },
1446         { "INT3430", LPSS_LPT_SSP },
1447         { "INT3431", LPSS_LPT_SSP },
1448         { "80860F0E", LPSS_BYT_SSP },
1449         { "8086228E", LPSS_BSW_SSP },
1450         { },
1451 };
1452 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1453 #endif
1454
1455 /*
1456  * PCI IDs of compound devices that integrate both host controller and private
1457  * integrated DMA engine. Please note these are not used in module
1458  * autoloading and probing in this module but matching the LPSS SSP type.
1459  */
1460 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1461         /* SPT-LP */
1462         { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1463         { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1464         /* SPT-H */
1465         { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1466         { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1467         /* KBL-H */
1468         { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1469         { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1470         /* CML-V */
1471         { PCI_VDEVICE(INTEL, 0xa3a9), LPSS_SPT_SSP },
1472         { PCI_VDEVICE(INTEL, 0xa3aa), LPSS_SPT_SSP },
1473         /* BXT A-Step */
1474         { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1475         { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1476         { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1477         /* BXT B-Step */
1478         { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1479         { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1480         { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1481         /* GLK */
1482         { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
1483         { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
1484         { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
1485         /* ICL-LP */
1486         { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
1487         { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
1488         { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
1489         /* EHL */
1490         { PCI_VDEVICE(INTEL, 0x4b2a), LPSS_BXT_SSP },
1491         { PCI_VDEVICE(INTEL, 0x4b2b), LPSS_BXT_SSP },
1492         { PCI_VDEVICE(INTEL, 0x4b37), LPSS_BXT_SSP },
1493         /* JSL */
1494         { PCI_VDEVICE(INTEL, 0x4daa), LPSS_CNL_SSP },
1495         { PCI_VDEVICE(INTEL, 0x4dab), LPSS_CNL_SSP },
1496         { PCI_VDEVICE(INTEL, 0x4dfb), LPSS_CNL_SSP },
1497         /* TGL-H */
1498         { PCI_VDEVICE(INTEL, 0x43aa), LPSS_CNL_SSP },
1499         { PCI_VDEVICE(INTEL, 0x43ab), LPSS_CNL_SSP },
1500         { PCI_VDEVICE(INTEL, 0x43fb), LPSS_CNL_SSP },
1501         { PCI_VDEVICE(INTEL, 0x43fd), LPSS_CNL_SSP },
1502         /* ADL-P */
1503         { PCI_VDEVICE(INTEL, 0x51aa), LPSS_CNL_SSP },
1504         { PCI_VDEVICE(INTEL, 0x51ab), LPSS_CNL_SSP },
1505         { PCI_VDEVICE(INTEL, 0x51fb), LPSS_CNL_SSP },
1506         /* ADL-M */
1507         { PCI_VDEVICE(INTEL, 0x54aa), LPSS_CNL_SSP },
1508         { PCI_VDEVICE(INTEL, 0x54ab), LPSS_CNL_SSP },
1509         { PCI_VDEVICE(INTEL, 0x54fb), LPSS_CNL_SSP },
1510         /* APL */
1511         { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1512         { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1513         { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1514         /* ADL-S */
1515         { PCI_VDEVICE(INTEL, 0x7aaa), LPSS_CNL_SSP },
1516         { PCI_VDEVICE(INTEL, 0x7aab), LPSS_CNL_SSP },
1517         { PCI_VDEVICE(INTEL, 0x7af9), LPSS_CNL_SSP },
1518         { PCI_VDEVICE(INTEL, 0x7afb), LPSS_CNL_SSP },
1519         /* CNL-LP */
1520         { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
1521         { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
1522         { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
1523         /* CNL-H */
1524         { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
1525         { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
1526         { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
1527         /* CML-LP */
1528         { PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP },
1529         { PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP },
1530         { PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP },
1531         /* CML-H */
1532         { PCI_VDEVICE(INTEL, 0x06aa), LPSS_CNL_SSP },
1533         { PCI_VDEVICE(INTEL, 0x06ab), LPSS_CNL_SSP },
1534         { PCI_VDEVICE(INTEL, 0x06fb), LPSS_CNL_SSP },
1535         /* TGL-LP */
1536         { PCI_VDEVICE(INTEL, 0xa0aa), LPSS_CNL_SSP },
1537         { PCI_VDEVICE(INTEL, 0xa0ab), LPSS_CNL_SSP },
1538         { PCI_VDEVICE(INTEL, 0xa0de), LPSS_CNL_SSP },
1539         { PCI_VDEVICE(INTEL, 0xa0df), LPSS_CNL_SSP },
1540         { PCI_VDEVICE(INTEL, 0xa0fb), LPSS_CNL_SSP },
1541         { PCI_VDEVICE(INTEL, 0xa0fd), LPSS_CNL_SSP },
1542         { PCI_VDEVICE(INTEL, 0xa0fe), LPSS_CNL_SSP },
1543         { },
1544 };
1545
1546 static const struct of_device_id pxa2xx_spi_of_match[] = {
1547         { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1548         {},
1549 };
1550 MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
1551
1552 #ifdef CONFIG_ACPI
1553
1554 static int pxa2xx_spi_get_port_id(struct device *dev)
1555 {
1556         struct acpi_device *adev;
1557         unsigned int devid;
1558         int port_id = -1;
1559
1560         adev = ACPI_COMPANION(dev);
1561         if (adev && adev->pnp.unique_id &&
1562             !kstrtouint(adev->pnp.unique_id, 0, &devid))
1563                 port_id = devid;
1564         return port_id;
1565 }
1566
1567 #else /* !CONFIG_ACPI */
1568
1569 static int pxa2xx_spi_get_port_id(struct device *dev)
1570 {
1571         return -1;
1572 }
1573
1574 #endif /* CONFIG_ACPI */
1575
1576
1577 #ifdef CONFIG_PCI
1578
1579 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1580 {
1581         return param == chan->device->dev;
1582 }
1583
1584 #endif /* CONFIG_PCI */
1585
1586 static struct pxa2xx_spi_controller *
1587 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1588 {
1589         struct pxa2xx_spi_controller *pdata;
1590         struct ssp_device *ssp;
1591         struct resource *res;
1592         struct device *parent = pdev->dev.parent;
1593         struct pci_dev *pcidev = dev_is_pci(parent) ? to_pci_dev(parent) : NULL;
1594         const struct pci_device_id *pcidev_id = NULL;
1595         enum pxa_ssp_type type;
1596         const void *match;
1597
1598         if (pcidev)
1599                 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, pcidev);
1600
1601         match = device_get_match_data(&pdev->dev);
1602         if (match)
1603                 type = (enum pxa_ssp_type)match;
1604         else if (pcidev_id)
1605                 type = (enum pxa_ssp_type)pcidev_id->driver_data;
1606         else
1607                 return ERR_PTR(-EINVAL);
1608
1609         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1610         if (!pdata)
1611                 return ERR_PTR(-ENOMEM);
1612
1613         ssp = &pdata->ssp;
1614
1615         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1616         ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1617         if (IS_ERR(ssp->mmio_base))
1618                 return ERR_CAST(ssp->mmio_base);
1619
1620         ssp->phys_base = res->start;
1621
1622 #ifdef CONFIG_PCI
1623         if (pcidev_id) {
1624                 pdata->tx_param = parent;
1625                 pdata->rx_param = parent;
1626                 pdata->dma_filter = pxa2xx_spi_idma_filter;
1627         }
1628 #endif
1629
1630         ssp->clk = devm_clk_get(&pdev->dev, NULL);
1631         if (IS_ERR(ssp->clk))
1632                 return ERR_CAST(ssp->clk);
1633
1634         ssp->irq = platform_get_irq(pdev, 0);
1635         if (ssp->irq < 0)
1636                 return ERR_PTR(ssp->irq);
1637
1638         ssp->type = type;
1639         ssp->dev = &pdev->dev;
1640         ssp->port_id = pxa2xx_spi_get_port_id(&pdev->dev);
1641
1642         pdata->is_slave = device_property_read_bool(&pdev->dev, "spi-slave");
1643         pdata->num_chipselect = 1;
1644         pdata->enable_dma = true;
1645         pdata->dma_burst_size = 1;
1646
1647         return pdata;
1648 }
1649
1650 static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1651                                       unsigned int cs)
1652 {
1653         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1654
1655         if (has_acpi_companion(&drv_data->pdev->dev)) {
1656                 switch (drv_data->ssp_type) {
1657                 /*
1658                  * For Atoms the ACPI DeviceSelection used by the Windows
1659                  * driver starts from 1 instead of 0 so translate it here
1660                  * to match what Linux expects.
1661                  */
1662                 case LPSS_BYT_SSP:
1663                 case LPSS_BSW_SSP:
1664                         return cs - 1;
1665
1666                 default:
1667                         break;
1668                 }
1669         }
1670
1671         return cs;
1672 }
1673
1674 static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
1675 {
1676         return MAX_DMA_LEN;
1677 }
1678
1679 static int pxa2xx_spi_probe(struct platform_device *pdev)
1680 {
1681         struct device *dev = &pdev->dev;
1682         struct pxa2xx_spi_controller *platform_info;
1683         struct spi_controller *controller;
1684         struct driver_data *drv_data;
1685         struct ssp_device *ssp;
1686         const struct lpss_config *config;
1687         int status, count;
1688         u32 tmp;
1689
1690         platform_info = dev_get_platdata(dev);
1691         if (!platform_info) {
1692                 platform_info = pxa2xx_spi_init_pdata(pdev);
1693                 if (IS_ERR(platform_info)) {
1694                         dev_err(&pdev->dev, "missing platform data\n");
1695                         return PTR_ERR(platform_info);
1696                 }
1697         }
1698
1699         ssp = pxa_ssp_request(pdev->id, pdev->name);
1700         if (!ssp)
1701                 ssp = &platform_info->ssp;
1702
1703         if (!ssp->mmio_base) {
1704                 dev_err(&pdev->dev, "failed to get ssp\n");
1705                 return -ENODEV;
1706         }
1707
1708         if (platform_info->is_slave)
1709                 controller = devm_spi_alloc_slave(dev, sizeof(*drv_data));
1710         else
1711                 controller = devm_spi_alloc_master(dev, sizeof(*drv_data));
1712
1713         if (!controller) {
1714                 dev_err(&pdev->dev, "cannot alloc spi_controller\n");
1715                 pxa_ssp_free(ssp);
1716                 return -ENOMEM;
1717         }
1718         drv_data = spi_controller_get_devdata(controller);
1719         drv_data->controller = controller;
1720         drv_data->controller_info = platform_info;
1721         drv_data->pdev = pdev;
1722         drv_data->ssp = ssp;
1723
1724         controller->dev.of_node = pdev->dev.of_node;
1725         /* the spi->mode bits understood by this driver: */
1726         controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1727
1728         controller->bus_num = ssp->port_id;
1729         controller->dma_alignment = DMA_ALIGNMENT;
1730         controller->cleanup = cleanup;
1731         controller->setup = setup;
1732         controller->set_cs = pxa2xx_spi_set_cs;
1733         controller->transfer_one = pxa2xx_spi_transfer_one;
1734         controller->slave_abort = pxa2xx_spi_slave_abort;
1735         controller->handle_err = pxa2xx_spi_handle_err;
1736         controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1737         controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1738         controller->auto_runtime_pm = true;
1739         controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1740
1741         drv_data->ssp_type = ssp->type;
1742
1743         drv_data->ioaddr = ssp->mmio_base;
1744         drv_data->ssdr_physical = ssp->phys_base + SSDR;
1745         if (pxa25x_ssp_comp(drv_data)) {
1746                 switch (drv_data->ssp_type) {
1747                 case QUARK_X1000_SSP:
1748                         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1749                         break;
1750                 default:
1751                         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1752                         break;
1753                 }
1754
1755                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1756                 drv_data->dma_cr1 = 0;
1757                 drv_data->clear_sr = SSSR_ROR;
1758                 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1759         } else {
1760                 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1761                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1762                 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1763                 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1764                 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1765                                                 | SSSR_ROR | SSSR_TUR;
1766         }
1767
1768         status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1769                         drv_data);
1770         if (status < 0) {
1771                 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1772                 goto out_error_controller_alloc;
1773         }
1774
1775         /* Setup DMA if requested */
1776         if (platform_info->enable_dma) {
1777                 status = pxa2xx_spi_dma_setup(drv_data);
1778                 if (status) {
1779                         dev_warn(dev, "no DMA channels available, using PIO\n");
1780                         platform_info->enable_dma = false;
1781                 } else {
1782                         controller->can_dma = pxa2xx_spi_can_dma;
1783                         controller->max_dma_len = MAX_DMA_LEN;
1784                         controller->max_transfer_size =
1785                                 pxa2xx_spi_max_dma_transfer_size;
1786                 }
1787         }
1788
1789         /* Enable SOC clock */
1790         status = clk_prepare_enable(ssp->clk);
1791         if (status)
1792                 goto out_error_dma_irq_alloc;
1793
1794         controller->max_speed_hz = clk_get_rate(ssp->clk);
1795         /*
1796          * Set minimum speed for all other platforms than Intel Quark which is
1797          * able do under 1 Hz transfers.
1798          */
1799         if (!pxa25x_ssp_comp(drv_data))
1800                 controller->min_speed_hz =
1801                         DIV_ROUND_UP(controller->max_speed_hz, 4096);
1802         else if (!is_quark_x1000_ssp(drv_data))
1803                 controller->min_speed_hz =
1804                         DIV_ROUND_UP(controller->max_speed_hz, 512);
1805
1806         /* Load default SSP configuration */
1807         pxa2xx_spi_write(drv_data, SSCR0, 0);
1808         switch (drv_data->ssp_type) {
1809         case QUARK_X1000_SSP:
1810                 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1811                       QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1812                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1813
1814                 /* using the Motorola SPI protocol and use 8 bit frame */
1815                 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1816                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1817                 break;
1818         case CE4100_SSP:
1819                 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1820                       CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1821                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1822                 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1823                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1824                 break;
1825         default:
1826
1827                 if (spi_controller_is_slave(controller)) {
1828                         tmp = SSCR1_SCFR |
1829                               SSCR1_SCLKDIR |
1830                               SSCR1_SFRMDIR |
1831                               SSCR1_RxTresh(2) |
1832                               SSCR1_TxTresh(1) |
1833                               SSCR1_SPH;
1834                 } else {
1835                         tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1836                               SSCR1_TxTresh(TX_THRESH_DFLT);
1837                 }
1838                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1839                 tmp = SSCR0_Motorola | SSCR0_DataSize(8);
1840                 if (!spi_controller_is_slave(controller))
1841                         tmp |= SSCR0_SCR(2);
1842                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1843                 break;
1844         }
1845
1846         if (!pxa25x_ssp_comp(drv_data))
1847                 pxa2xx_spi_write(drv_data, SSTO, 0);
1848
1849         if (!is_quark_x1000_ssp(drv_data))
1850                 pxa2xx_spi_write(drv_data, SSPSP, 0);
1851
1852         if (is_lpss_ssp(drv_data)) {
1853                 lpss_ssp_setup(drv_data);
1854                 config = lpss_get_config(drv_data);
1855                 if (config->reg_capabilities >= 0) {
1856                         tmp = __lpss_ssp_read_priv(drv_data,
1857                                                    config->reg_capabilities);
1858                         tmp &= LPSS_CAPS_CS_EN_MASK;
1859                         tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1860                         platform_info->num_chipselect = ffz(tmp);
1861                 } else if (config->cs_num) {
1862                         platform_info->num_chipselect = config->cs_num;
1863                 }
1864         }
1865         controller->num_chipselect = platform_info->num_chipselect;
1866
1867         count = gpiod_count(&pdev->dev, "cs");
1868         if (count > 0) {
1869                 int i;
1870
1871                 controller->num_chipselect = max_t(int, count,
1872                         controller->num_chipselect);
1873
1874                 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
1875                         controller->num_chipselect, sizeof(struct gpio_desc *),
1876                         GFP_KERNEL);
1877                 if (!drv_data->cs_gpiods) {
1878                         status = -ENOMEM;
1879                         goto out_error_clock_enabled;
1880                 }
1881
1882                 for (i = 0; i < controller->num_chipselect; i++) {
1883                         struct gpio_desc *gpiod;
1884
1885                         gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1886                         if (IS_ERR(gpiod)) {
1887                                 /* Means use native chip select */
1888                                 if (PTR_ERR(gpiod) == -ENOENT)
1889                                         continue;
1890
1891                                 status = PTR_ERR(gpiod);
1892                                 goto out_error_clock_enabled;
1893                         } else {
1894                                 drv_data->cs_gpiods[i] = gpiod;
1895                         }
1896                 }
1897         }
1898
1899         if (platform_info->is_slave) {
1900                 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1901                                                 "ready", GPIOD_OUT_LOW);
1902                 if (IS_ERR(drv_data->gpiod_ready)) {
1903                         status = PTR_ERR(drv_data->gpiod_ready);
1904                         goto out_error_clock_enabled;
1905                 }
1906         }
1907
1908         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1909         pm_runtime_use_autosuspend(&pdev->dev);
1910         pm_runtime_set_active(&pdev->dev);
1911         pm_runtime_enable(&pdev->dev);
1912
1913         /* Register with the SPI framework */
1914         platform_set_drvdata(pdev, drv_data);
1915         status = spi_register_controller(controller);
1916         if (status != 0) {
1917                 dev_err(&pdev->dev, "problem registering spi controller\n");
1918                 goto out_error_pm_runtime_enabled;
1919         }
1920
1921         return status;
1922
1923 out_error_pm_runtime_enabled:
1924         pm_runtime_disable(&pdev->dev);
1925
1926 out_error_clock_enabled:
1927         clk_disable_unprepare(ssp->clk);
1928
1929 out_error_dma_irq_alloc:
1930         pxa2xx_spi_dma_release(drv_data);
1931         free_irq(ssp->irq, drv_data);
1932
1933 out_error_controller_alloc:
1934         pxa_ssp_free(ssp);
1935         return status;
1936 }
1937
1938 static int pxa2xx_spi_remove(struct platform_device *pdev)
1939 {
1940         struct driver_data *drv_data = platform_get_drvdata(pdev);
1941         struct ssp_device *ssp = drv_data->ssp;
1942
1943         pm_runtime_get_sync(&pdev->dev);
1944
1945         spi_unregister_controller(drv_data->controller);
1946
1947         /* Disable the SSP at the peripheral and SOC level */
1948         pxa2xx_spi_write(drv_data, SSCR0, 0);
1949         clk_disable_unprepare(ssp->clk);
1950
1951         /* Release DMA */
1952         if (drv_data->controller_info->enable_dma)
1953                 pxa2xx_spi_dma_release(drv_data);
1954
1955         pm_runtime_put_noidle(&pdev->dev);
1956         pm_runtime_disable(&pdev->dev);
1957
1958         /* Release IRQ */
1959         free_irq(ssp->irq, drv_data);
1960
1961         /* Release SSP */
1962         pxa_ssp_free(ssp);
1963
1964         return 0;
1965 }
1966
1967 #ifdef CONFIG_PM_SLEEP
1968 static int pxa2xx_spi_suspend(struct device *dev)
1969 {
1970         struct driver_data *drv_data = dev_get_drvdata(dev);
1971         struct ssp_device *ssp = drv_data->ssp;
1972         int status;
1973
1974         status = spi_controller_suspend(drv_data->controller);
1975         if (status != 0)
1976                 return status;
1977         pxa2xx_spi_write(drv_data, SSCR0, 0);
1978
1979         if (!pm_runtime_suspended(dev))
1980                 clk_disable_unprepare(ssp->clk);
1981
1982         return 0;
1983 }
1984
1985 static int pxa2xx_spi_resume(struct device *dev)
1986 {
1987         struct driver_data *drv_data = dev_get_drvdata(dev);
1988         struct ssp_device *ssp = drv_data->ssp;
1989         int status;
1990
1991         /* Enable the SSP clock */
1992         if (!pm_runtime_suspended(dev)) {
1993                 status = clk_prepare_enable(ssp->clk);
1994                 if (status)
1995                         return status;
1996         }
1997
1998         /* Start the queue running */
1999         return spi_controller_resume(drv_data->controller);
2000 }
2001 #endif
2002
2003 #ifdef CONFIG_PM
2004 static int pxa2xx_spi_runtime_suspend(struct device *dev)
2005 {
2006         struct driver_data *drv_data = dev_get_drvdata(dev);
2007
2008         clk_disable_unprepare(drv_data->ssp->clk);
2009         return 0;
2010 }
2011
2012 static int pxa2xx_spi_runtime_resume(struct device *dev)
2013 {
2014         struct driver_data *drv_data = dev_get_drvdata(dev);
2015         int status;
2016
2017         status = clk_prepare_enable(drv_data->ssp->clk);
2018         return status;
2019 }
2020 #endif
2021
2022 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
2023         SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
2024         SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
2025                            pxa2xx_spi_runtime_resume, NULL)
2026 };
2027
2028 static struct platform_driver driver = {
2029         .driver = {
2030                 .name   = "pxa2xx-spi",
2031                 .pm     = &pxa2xx_spi_pm_ops,
2032                 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
2033                 .of_match_table = of_match_ptr(pxa2xx_spi_of_match),
2034         },
2035         .probe = pxa2xx_spi_probe,
2036         .remove = pxa2xx_spi_remove,
2037 };
2038
2039 static int __init pxa2xx_spi_init(void)
2040 {
2041         return platform_driver_register(&driver);
2042 }
2043 subsys_initcall(pxa2xx_spi_init);
2044
2045 static void __exit pxa2xx_spi_exit(void)
2046 {
2047         platform_driver_unregister(&driver);
2048 }
2049 module_exit(pxa2xx_spi_exit);
2050
2051 MODULE_SOFTDEP("pre: dw_dmac");